[llvm] r320322 - [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Dec 10 11:19:22 2017
New Revision: 320322

URL: http://llvm.org/viewvc/llvm-project?rev=320322&view=rev
Log:
[X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
    llvm/trunk/test/CodeGen/X86/x87-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=320322&r1=320321&r2=320322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sun Dec 10 11:19:22 2017
@@ -739,7 +739,7 @@ def : InstRW<[ZnWriteFILD], (instregex "
 def ZnWriteFIST : SchedWriteRes<[ZnAGU, ZnFPU23]> {
   let Latency = 12;
 }
-def : InstRW<[ZnWriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
+def : InstRW<[ZnWriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>;
 
 def ZnWriteFPU13 : SchedWriteRes<[ZnAGU, ZnFPU13]> {
   let Latency = 8;

Modified: llvm/trunk/test/CodeGen/X86/x87-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x87-schedule.ll?rev=320322&r1=320321&r2=320322&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x87-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x87-schedule.ll Sun Dec 10 11:19:22 2017
@@ -2581,10 +2581,10 @@ define void @test_fist_fistp_fisttp(i16*
 ; ZNVER1-NEXT:    fistl (%ecx) # sched: [12:0.50]
 ; ZNVER1-NEXT:    fistps (%edx) # sched: [12:0.50]
 ; ZNVER1-NEXT:    fistpl (%ecx) # sched: [12:0.50]
-; ZNVER1-NEXT:    fistpll (%eax) # sched: [1:0.50]
-; ZNVER1-NEXT:    fisttps (%edx) # sched: [1:0.50]
-; ZNVER1-NEXT:    fisttpl (%ecx) # sched: [1:0.50]
-; ZNVER1-NEXT:    fisttpll (%eax) # sched: [1:0.50]
+; ZNVER1-NEXT:    fistpll (%eax) # sched: [12:0.50]
+; ZNVER1-NEXT:    fisttps (%edx) # sched: [12:0.50]
+; ZNVER1-NEXT:    fisttpl (%ecx) # sched: [12:0.50]
+; ZNVER1-NEXT:    fisttpll (%eax) # sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fists $0 \0A\09 fistl $1 \0A\09 fistps $0 \0A\09 fistpl $1 \0A\09 fistpll $2 \0A\09 fisttps $0 \0A\09 fisttpl $1 \0A\09 fisttpll $2", "*m,*m,*m"(i16* %a0, i32* %a1, i64 *%a2) nounwind