[llvm] r320313 - [X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Dec 10 09:42:36 2017
New Revision: 320313

URL: http://llvm.org/viewvc/llvm-project?rev=320313&view=rev
Log:
[X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs.

This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86Schedule.td

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=320313&r1=320312&r2=320313&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Sun Dec 10 09:42:36 2017
@@ -324,10 +324,34 @@ def FeatureHasFastGather
                        "Indicates if gather is reasonably fast.">;
 
 //===----------------------------------------------------------------------===//
-// X86 processors supported.
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "X86RegisterInfo.td"
+include "X86RegisterBanks.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "X86Schedule.td"
+include "X86InstrInfo.td"
+
+def X86InstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// X86 processors supported.
+//===----------------------------------------------------------------------===//
+
+include "X86ScheduleAtom.td"
+include "X86SchedSandyBridge.td"
+include "X86SchedHaswell.td"
+include "X86SchedBroadwell.td"
+include "X86ScheduleSLM.td"
+include "X86ScheduleZnver1.td"
+include "X86ScheduleBtVer2.td"
+include "X86SchedSkylakeClient.td"
+include "X86SchedSkylakeServer.td"
 
 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
                     "Intel Atom processors">;
@@ -955,21 +979,6 @@ def : ProcessorModel<"x86-64", SandyBrid
 ]>;
 
 //===----------------------------------------------------------------------===//
-// Register File Description
-//===----------------------------------------------------------------------===//
-
-include "X86RegisterInfo.td"
-include "X86RegisterBanks.td"
-
-//===----------------------------------------------------------------------===//
-// Instruction Descriptions
-//===----------------------------------------------------------------------===//
-
-include "X86InstrInfo.td"
-
-def X86InstrInfo : InstrInfo;
-
-//===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=320313&r1=320312&r2=320313&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Sun Dec 10 09:42:36 2017
@@ -692,13 +692,3 @@ def GenericPostRAModel : GenericX86Model
   let PostRAScheduler = 1;
 }
 
-include "X86ScheduleAtom.td"
-include "X86SchedSandyBridge.td"
-include "X86SchedHaswell.td"
-include "X86SchedBroadwell.td"
-include "X86ScheduleSLM.td"
-include "X86ScheduleZnver1.td"
-include "X86ScheduleBtVer2.td"
-include "X86SchedSkylakeClient.td"
-include "X86SchedSkylakeServer.td"
-