[llvm] r320304 - [X86] Flag ZNVER1 scheduler model as complete

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Dec 10 04:43:53 2017
New Revision: 320304

URL: http://llvm.org/viewvc/llvm-project?rev=320304&view=rev
Log:
[X86] Flag ZNVER1 scheduler model as complete

We just have to locally tag COPY as WriteMove

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=320304&r1=320303&r2=320304&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sun Dec 10 04:43:53 2017
@@ -21,12 +21,6 @@ def Znver1Model : SchedMachineModel {
   let MispredictPenalty = 17;
   let HighLatency = 25;
   let PostRAScheduler = 1;
-
-  // FIXME: This variable is required for incomplete model.
-  // We haven't catered all instructions.
-  // So, we reset the value of this variable so as to
-  // say that the model is incomplete.
-  let CompleteModel = 0;
 }
 
 let SchedModel = Znver1Model in {
@@ -140,6 +134,9 @@ defm : ZnWriteResPair<WriteALU,   ZnALU,
 defm : ZnWriteResPair<WriteShift, ZnALU, 1>;
 defm : ZnWriteResPair<WriteJump,  ZnALU, 1>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 // IDIV
 def : WriteRes<WriteIDiv, [ZnALU2, ZnDivider]> {
   let Latency = 41;