[llvm] r320296 - [X86] Tag MORESTACK instructions as ret scheduler class

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Dec 10 02:08:21 2017
New Revision: 320296

URL: http://llvm.org/viewvc/llvm-project?rev=320296&view=rev
Log:
[X86] Tag MORESTACK instructions as ret scheduler class

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=320296&r1=320295&r2=320296&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sun Dec 10 02:08:21 2017
@@ -257,15 +257,15 @@ let isPseudo = 1, SchedRW = [WriteSystem
 // This is lowered into a RET instruction by MCInstLower.  We need
 // this so that we don't have to have a MachineBasicBlock which ends
 // with a RET and also has successors.
-let isPseudo = 1 in {
+let isPseudo = 1, SchedRW = [WriteJumpLd] in {
 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
-                          "", []>;
+                          "", [], IIC_RET>;
 
 // This instruction is lowered to a RET followed by a MOV.  The two
 // instructions are not generated on a higher level since then the
 // verifier sees a MachineBasicBlock ending with a non-terminator.
 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
-                                  "", []>;
+                                  "", [], IIC_RET>;
 }
 
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