[llvm] r320293 - [X86] Add LEA64_32r to scheduler models for Sandybridge, Haswell, Broadwell, Skylake

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Dec 10 01:14:42 2017
New Revision: 320293

URL: http://llvm.org/viewvc/llvm-project?rev=320293&view=rev
Log:
[X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake

Modified:
    llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
    llvm/trunk/lib/Target/X86/X86SchedHaswell.td
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=320293&r1=320292&r2=320293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Dec 10 01:14:42 2017
@@ -708,7 +708,7 @@ def: InstRW<[BWWriteResGroup7], (instreg
 def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>;
 def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>;
 def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>;
 def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;
 def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;
 def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=320293&r1=320292&r2=320293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Dec 10 01:14:42 2017
@@ -1252,7 +1252,7 @@ def: InstRW<[HWWriteResGroup8], (instreg
 def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
 def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
 def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=320293&r1=320292&r2=320293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Dec 10 01:14:42 2017
@@ -469,7 +469,7 @@ def SBWriteResGroup3 : SchedWriteRes<[SB
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
 
 def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
   let Latency = 1;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=320293&r1=320292&r2=320293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Dec 10 01:14:42 2017
@@ -821,7 +821,7 @@ def: InstRW<[SKLWriteResGroup8], (instre
 def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;
 def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;
 def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
 
 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
   let Latency = 1;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=320293&r1=320292&r2=320293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Dec 10 01:14:42 2017
@@ -1124,7 +1124,7 @@ def: InstRW<[SKXWriteResGroup8], (instre
 def: InstRW<[SKXWriteResGroup8], (instregex "BLSR64rr")>;
 def: InstRW<[SKXWriteResGroup8], (instregex "BZHI32rr")>;
 def: InstRW<[SKXWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
 
 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
   let Latency = 1;