[llvm] r320265 - Strip trailing whitespace. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Dec  9 12:44:51 2017
New Revision: 320265

URL: http://llvm.org/viewvc/llvm-project?rev=320265&view=rev
Log:
Strip trailing whitespace. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/lib/Target/X86/X86InstrSystem.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=320265&r1=320264&r2=320265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sat Dec  9 12:44:51 2017
@@ -803,7 +803,7 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MR
 // register and the register allocator will ignore any use/def of
 // it. In other words, the register will not fix the clobbering of
 // RBX that will happen when setting the arguments for the instrucion.
-// 
+//
 // Unlike the actual related instuction, we mark that this one
 // defines EBX (instead of using EBX).
 // The rationale is that we will define RBX during the expansion of

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=320265&r1=320264&r2=320265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Sat Dec  9 12:44:51 2017
@@ -489,24 +489,24 @@ let SchedRW = [WriteSystem], Predicates
       def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
                        [(int_x86_incsspd GR32:$src)]>, XS;
       def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
-                       [(int_x86_incsspq GR64:$src)]>, XS, 
+                       [(int_x86_incsspq GR64:$src)]>, XS,
                        Requires<[In64BitMode]>;
     } // Defs SSP
 
     let Constraints = "$src = $dst" in {
-      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 
+      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
                      "rdsspd\t$dst",
                      [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
-      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 
-                     "rdsspq\t$dst", 
-                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS, 
+      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
+                     "rdsspq\t$dst",
+                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS,
                      Requires<[In64BitMode]>;
     }
 
     let Defs = [SSP] in {
       def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
                        [(int_x86_saveprevssp)]>, XS;
-      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), 
+      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
                        "rstorssp\t$src",
                        [(int_x86_rstorssp addr:$src)]>, XS;
     } // Defs SSP
@@ -517,14 +517,14 @@ let SchedRW = [WriteSystem], Predicates
                 [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8;
   def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
                  "wrssq\t{$src, $dst|$dst, $src}",
-                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8, 
+                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8,
                  Requires<[In64BitMode]>;
   def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
                  "wrussd\t{$src, $dst|$dst, $src}",
                  [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
-  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 
+  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
                   "wrussq\t{$src, $dst|$dst, $src}",
-                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD, 
+                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD,
                   Requires<[In64BitMode]>;
 
   let Defs = [SSP] in {
@@ -533,7 +533,7 @@ let SchedRW = [WriteSystem], Predicates
                          [(int_x86_setssbsy)]>, XS;
     } // Uses SSP
 
-    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), 
+    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
                      "clrssbsy\t$src",
                      [(int_x86_clrssbsy addr:$src)]>, XS;
   } // Defs SSP
@@ -547,8 +547,8 @@ let Defs = [EDX, EAX], Uses = [ECX] in
   def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
 
 let Uses = [EDX, EAX, ECX] in
-  def XSETBV : I<0x01, MRM_D1, (outs), (ins), 
-                "xsetbv", 
+  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
+                "xsetbv",
                 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
 
 } // HasXSAVE