[llvm] r320209 - [CodeGen] Move printing MO_Immediate operands to MachineOperand::print
Francis Visoiu Mistrih via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 8 14:53:21 PST 2017
Author: thegameg
Date: Fri Dec 8 14:53:21 2017
New Revision: 320209
URL: http://llvm.org/viewvc/llvm-project?rev=320209&view=rev
Log:
[CodeGen] Move printing MO_Immediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
Add support for operand subreg index as an immediate to debug printing
and use ::print in the MIRPrinter.
Differential Review: https://reviews.llvm.org/D40965
Modified:
llvm/trunk/docs/MIRLangRef.rst
llvm/trunk/include/llvm/CodeGen/MachineOperand.h
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineOperand.cpp
llvm/trunk/unittests/CodeGen/MachineOperandTest.cpp
Modified: llvm/trunk/docs/MIRLangRef.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/MIRLangRef.rst?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/docs/MIRLangRef.rst (original)
+++ llvm/trunk/docs/MIRLangRef.rst Fri Dec 8 14:53:21 2017
@@ -430,6 +430,35 @@ immediate machine operand ``-42``:
%eax = MOV32ri -42
+An immediate operand is also used to represent a subregister index when the
+machine instruction has one of the following opcodes:
+
+- ``EXTRACT_SUBREG``
+
+- ``INSERT_SUBREG``
+
+- ``REG_SEQUENCE``
+
+- ``SUBREG_TO_REG``
+
+In case this is true, the Machine Operand is printed according to the target.
+
+For example:
+
+In AArch64RegisterInfo.td:
+
+.. code-block:: text
+
+ def sub_32 : SubRegIndex<32>;
+
+If the third operand is an immediate with the value ``15`` (target-dependent
+value), based on the instruction's opcode and the operand's index the operand
+will be printed as ``%subreg.sub_32``:
+
+.. code-block:: text
+
+ %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
+
For integers > 64bit, we use a special machine operand, ``MO_CImmediate``,
which stores the immediate in a ``ConstantInt`` using an ``APInt`` (LLVM's
arbitrary precision integers).
Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Fri Dec 8 14:53:21 2017
@@ -227,6 +227,13 @@ public:
///
void clearParent() { ParentMI = nullptr; }
+ /// Print a subreg index operand.
+ /// MO_Immediate operands can also be subreg idices. If it's the case, the
+ /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
+ /// called to check this.
+ static void printSubregIdx(raw_ostream &OS, uint64_t Index,
+ const TargetRegisterInfo *TRI);
+
/// Print the MachineOperand to \p os.
/// Providing a valid \p TRI and \p IntrinsicInfo results in a more
/// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Fri Dec 8 14:53:21 2017
@@ -854,23 +854,23 @@ void MIPrinter::print(const MachineInstr
const MachineOperand &Op = MI.getOperand(OpIdx);
printTargetFlags(Op);
switch (Op.getType()) {
+ case MachineOperand::MO_Immediate:
+ if (MI.isOperandSubregIdx(OpIdx)) {
+ MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
+ break;
+ }
+ LLVM_FALLTHROUGH;
case MachineOperand::MO_Register:
case MachineOperand::MO_CImmediate:
case MachineOperand::MO_MachineBasicBlock: {
unsigned TiedOperandIdx = 0;
- if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
+ if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
TiedOperandIdx, TRI, TII);
break;
}
- case MachineOperand::MO_Immediate:
- if (MI.isOperandSubregIdx(OpIdx))
- OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm());
- else
- OS << Op.getImm();
- break;
case MachineOperand::MO_FPImmediate:
Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
break;
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Dec 8 14:53:21 2017
@@ -1405,8 +1405,11 @@ void MachineInstr::print(raw_ostream &OS
} else {
LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(i);
- MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, ShouldPrintRegisterTies,
- TiedOperandIdx, TRI, IntrinsicInfo);
+ if (MO.isImm() && isOperandSubregIdx(i))
+ MachineOperand::printSubregIdx(OS, MO.getImm(), TRI);
+ else
+ MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
+ ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
}
}
Modified: llvm/trunk/lib/CodeGen/MachineOperand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOperand.cpp?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineOperand.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineOperand.cpp Fri Dec 8 14:53:21 2017
@@ -345,6 +345,15 @@ static void tryToGetTargetInfo(const Mac
}
}
+void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
+ const TargetRegisterInfo *TRI) {
+ OS << "%subreg.";
+ if (TRI)
+ OS << TRI->getSubRegIndexName(Index);
+ else
+ OS << Index;
+}
+
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
Modified: llvm/trunk/unittests/CodeGen/MachineOperandTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineOperandTest.cpp?rev=320209&r1=320208&r2=320209&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/MachineOperandTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/MachineOperandTest.cpp Fri Dec 8 14:53:21 2017
@@ -11,6 +11,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/Support/raw_ostream.h"
#include "gtest/gtest.h"
@@ -100,4 +101,22 @@ TEST(MachineOperandTest, PrintCImm) {
ASSERT_TRUE(OS.str() == "i128 18446744073709551616");
}
+TEST(MachineOperandTest, PrintSubRegIndex) {
+ // Create a MachineOperand with an immediate and print it as a subreg index.
+ MachineOperand MO = MachineOperand::CreateImm(3);
+
+ // Checking some preconditions on the newly created
+ // MachineOperand.
+ ASSERT_TRUE(MO.isImm());
+ ASSERT_TRUE(MO.getImm() == 3);
+
+ // Print a MachineOperand containing a SubRegIdx. Here we check that without a
+ // TRI and IntrinsicInfo we can print the operand as a subreg index.
+ std::string str;
+ raw_string_ostream OS(str);
+ ModuleSlotTracker DummyMST(nullptr);
+ MachineOperand::printSubregIdx(OS, MO.getImm(), nullptr);
+ ASSERT_TRUE(OS.str() == "%subreg.3");
+}
+
} // end namespace
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