[PATCH] D40985: [AArch64] Add Exynos to host detection
Evandro Menezes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 8 13:10:48 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL320195: [AArch64] Add Exynos to host detection (authored by evandro).
Changed prior to commit:
https://reviews.llvm.org/D40985?vs=126053&id=126200#toc
Repository:
rL LLVM
https://reviews.llvm.org/D40985
Files:
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/unittests/Support/Host.cpp
Index: llvm/trunk/lib/Support/Host.cpp
===================================================================
--- llvm/trunk/lib/Support/Host.cpp
+++ llvm/trunk/lib/Support/Host.cpp
@@ -216,6 +216,37 @@
.Case("0xc01", "saphira")
.Default("generic");
+ if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
+ // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
+ // any predictive pattern across variants and parts.
+ unsigned Variant = 0, Part = 0;
+
+ // Look for the CPU variant line, whose value is a 1 digit hexadecimal
+ // number, corresponding to the Variant bits in the CP15/C0 register.
+ for (auto I : Lines)
+ if (I.consume_front("CPU variant"))
+ I.ltrim("\t :").getAsInteger(0, Variant);
+
+ // Look for the CPU part line, whose value is a 3 digit hexadecimal
+ // number, corresponding to the PartNum bits in the CP15/C0 register.
+ for (auto I : Lines)
+ if (I.consume_front("CPU part"))
+ I.ltrim("\t :").getAsInteger(0, Part);
+
+ unsigned Exynos = (Variant << 12) | Part;
+ switch (Exynos) {
+ default:
+ // Default by falling through to Exynos M1.
+ LLVM_FALLTHROUGH;
+
+ case 0x1001:
+ return "exynos-m1";
+
+ case 0x4001:
+ return "exynos-m2";
+ }
+ }
+
return "generic";
}
Index: llvm/trunk/unittests/Support/Host.cpp
===================================================================
--- llvm/trunk/unittests/Support/Host.cpp
+++ llvm/trunk/unittests/Support/Host.cpp
@@ -139,6 +139,37 @@
EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo),
"cortex-a53");
+
+ // Exynos big.LITTLE weirdness
+ const std::string ExynosProcCpuInfo = R"(
+processor : 0
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd03
+
+processor : 1
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
+CPU implementer : 0x53
+CPU architecture: 8
+)";
+
+ // Verify default for Exynos.
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
+ "CPU variant : 0xc\n"
+ "CPU part : 0xafe"),
+ "exynos-m1");
+ // Verify Exynos M1.
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
+ "CPU variant : 0x1\n"
+ "CPU part : 0x001"),
+ "exynos-m1");
+ // Verify Exynos M2.
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
+ "CPU variant : 0x4\n"
+ "CPU part : 0x001"),
+ "exynos-m2");
}
#if defined(__APPLE__)
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