[llvm] r320189 - [X86][X87] Tag x87 float compare instructions scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 8 12:10:32 PST 2017
Author: rksimon
Date: Fri Dec 8 12:10:31 2017
New Revision: 320189
URL: http://llvm.org/viewvc/llvm-project?rev=320189&view=rev
Log:
[X86][X87] Tag x87 float compare instructions scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrFPStack.td
llvm/trunk/test/CodeGen/X86/x87-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=320189&r1=320188&r2=320189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Fri Dec 8 12:10:31 2017
@@ -281,6 +281,8 @@ def SUB_FPrST0 : FPrST0PInst<MRM5r, "fs
def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
+def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
+def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
} // SchedRW
let SchedRW = [WriteFMul] in {
def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;
@@ -296,9 +298,6 @@ def DIVR_FrST0 : FPrST0Inst <MRM6r, "fd
def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
} // SchedRW
-def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
-def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
-
// Unary operations.
multiclass FPUnary<SDNode OpNode, Format fp, string asmstring,
InstrItinClass itin> {
@@ -326,39 +325,44 @@ defm SIN : FPUnary<fsin, MRM_FE, "fsin",
defm COS : FPUnary<fcos, MRM_FF, "fcos", IIC_FSINCOS>;
}
+let SchedRW = [WriteFAdd] in {
let hasSideEffects = 0 in {
def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
} // hasSideEffects
-let SchedRW = [WriteFAdd] in
def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst", IIC_FCOMI>;
+} // SchedRW
} // Defs = [FPSW]
// Versions of FP instructions that take a single memory operand. Added for the
// disassembler; remove as they are included with patterns elsewhere.
+let SchedRW = [WriteFAddLd] in {
def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
-def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
-def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
+def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
+def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
+
+def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
+def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
+} // SchedRW
-def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
-def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
+let SchedRW = [WriteMicrocoded] in {
+def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
+def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;
def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
-def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
-def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
-
def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
+} // SchedRW
// Floating point cmovs.
class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern,
Modified: llvm/trunk/test/CodeGen/X86/x87-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x87-schedule.ll?rev=320189&r1=320188&r2=320189&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x87-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x87-schedule.ll Fri Dec 8 12:10:31 2017
@@ -752,10 +752,10 @@ define void @test_fcom(float *%a0, doubl
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
-; SLM-NEXT: fcom %st(1)
-; SLM-NEXT: fcom %st(3)
-; SLM-NEXT: fcoms (%ecx)
-; SLM-NEXT: fcoml (%eax)
+; SLM-NEXT: fcom %st(1) # sched: [3:1.00]
+; SLM-NEXT: fcom %st(3) # sched: [3:1.00]
+; SLM-NEXT: fcoms (%ecx) # sched: [6:1.00]
+; SLM-NEXT: fcoml (%eax) # sched: [6:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@@ -824,10 +824,10 @@ define void @test_fcom(float *%a0, doubl
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: fcom %st(1)
-; BTVER2-NEXT: fcom %st(3)
-; BTVER2-NEXT: fcoms (%ecx)
-; BTVER2-NEXT: fcoml (%eax)
+; BTVER2-NEXT: fcom %st(1) # sched: [3:1.00]
+; BTVER2-NEXT: fcom %st(3) # sched: [3:1.00]
+; BTVER2-NEXT: fcoms (%ecx) # sched: [8:1.00]
+; BTVER2-NEXT: fcoml (%eax) # sched: [8:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
@@ -878,10 +878,10 @@ define void @test_fcomp_fcompp(float *%a
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
-; SLM-NEXT: fcomp %st(1)
-; SLM-NEXT: fcomp %st(3)
-; SLM-NEXT: fcomps (%ecx)
-; SLM-NEXT: fcompl (%eax)
+; SLM-NEXT: fcomp %st(1) # sched: [3:1.00]
+; SLM-NEXT: fcomp %st(3) # sched: [3:1.00]
+; SLM-NEXT: fcomps (%ecx) # sched: [6:1.00]
+; SLM-NEXT: fcompl (%eax) # sched: [6:1.00]
; SLM-NEXT: fcompp # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
@@ -956,10 +956,10 @@ define void @test_fcomp_fcompp(float *%a
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: fcomp %st(1)
-; BTVER2-NEXT: fcomp %st(3)
-; BTVER2-NEXT: fcomps (%ecx)
-; BTVER2-NEXT: fcompl (%eax)
+; BTVER2-NEXT: fcomp %st(1) # sched: [3:1.00]
+; BTVER2-NEXT: fcomp %st(3) # sched: [3:1.00]
+; BTVER2-NEXT: fcomps (%ecx) # sched: [8:1.00]
+; BTVER2-NEXT: fcompl (%eax) # sched: [8:1.00]
; BTVER2-NEXT: fcompp # sched: [100:0.17]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
@@ -1812,10 +1812,10 @@ define void @test_ficom(i16 *%a0, i32 *%
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
-; SLM-NEXT: ficoms (%ecx)
-; SLM-NEXT: ficoml (%eax)
-; SLM-NEXT: ficomps (%ecx)
-; SLM-NEXT: ficompl (%eax)
+; SLM-NEXT: ficoms (%ecx) # sched: [6:1.00]
+; SLM-NEXT: ficoml (%eax) # sched: [6:1.00]
+; SLM-NEXT: ficomps (%ecx) # sched: [6:1.00]
+; SLM-NEXT: ficompl (%eax) # sched: [6:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@@ -1884,10 +1884,10 @@ define void @test_ficom(i16 *%a0, i32 *%
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: ficoms (%ecx)
-; BTVER2-NEXT: ficoml (%eax)
-; BTVER2-NEXT: ficomps (%ecx)
-; BTVER2-NEXT: ficompl (%eax)
+; BTVER2-NEXT: ficoms (%ecx) # sched: [8:1.00]
+; BTVER2-NEXT: ficoml (%eax) # sched: [8:1.00]
+; BTVER2-NEXT: ficomps (%ecx) # sched: [8:1.00]
+; BTVER2-NEXT: ficompl (%eax) # sched: [8:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
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