[llvm] r320154 - [X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Dec  8 07:17:32 2017
New Revision: 320154

URL: http://llvm.org/viewvc/llvm-project?rev=320154&view=rev
Log:
[X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classes

Match VPTERNLOG which these pseudos will eventually alias to

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=320154&r1=320153&r2=320154&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Fri Dec  8 07:17:32 2017
@@ -453,7 +453,7 @@ def AVX512_512_SETALLONES : I<0, Pseudo,
 // Alias instructions that allow VPTERNLOG to be used with a mask to create
 // a mix of all ones and all zeros elements. This is done this way to force
 // the same register to be used as input for all three sources.
-let isPseudo = 1, Predicates = [HasAVX512] in {
+let isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteVecALU] in {
 def AVX512_512_SEXT_MASK_32 : I<0, Pseudo, (outs VR512:$dst),
                                 (ins VK16WM:$mask), "",
                            [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask),