[llvm] r320055 - [X86] Tag SALC instructions scheduler class
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 7 08:07:07 PST 2017
Author: rksimon
Date: Thu Dec 7 08:07:06 2017
New Revision: 320055
URL: http://llvm.org/viewvc/llvm-project?rev=320055&view=rev
Log:
[X86] Tag SALC instructions scheduler class
Treat these the same as LAHF/SAHF (although its not a x86_64 instruction)
Modified:
llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td
llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td?rev=320055&r1=320054&r2=320055&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td Thu Dec 7 08:07:06 2017
@@ -113,6 +113,6 @@ defm SETG : SETCC<0x9F, "setg", X86_CO
// SALC is an undocumented instruction. Information for this instruction can be found
// here http://www.rcollins.org/secrets/opcodes/SALC.html
// Set AL if carry.
-let Uses = [EFLAGS], Defs = [AL] in {
- def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
+let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
+ def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", [], IIC_AHF>, Requires<[Not64BitMode]>;
}
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll?rev=320055&r1=320054&r2=320055&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll Thu Dec 7 08:07:06 2017
@@ -528,63 +528,63 @@ define i8 @test_salc() optsize {
; ATOM-LABEL: test_salc:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
-; ATOM-NEXT: salc
+; ATOM-NEXT: salc # sched: [1:0.50]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_salc:
; SLM: # %bb.0:
; SLM-NEXT: #APP
-; SLM-NEXT: salc
+; SLM-NEXT: salc # sched: [1:0.50]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_salc:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
-; SANDY-NEXT: salc
+; SANDY-NEXT: salc # sched: [1:0.33]
; SANDY-NEXT: #NO_APP
; SANDY-NEXT: retl # sched: [5:1.00]
;
; HASWELL-LABEL: test_salc:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
-; HASWELL-NEXT: salc
+; HASWELL-NEXT: salc # sched: [1:0.25]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [5:0.50]
;
; BROADWELL-LABEL: test_salc:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
-; BROADWELL-NEXT: salc
+; BROADWELL-NEXT: salc # sched: [1:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_salc:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
-; SKYLAKE-NEXT: salc
+; SKYLAKE-NEXT: salc # sched: [1:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_salc:
; SKX: # %bb.0:
; SKX-NEXT: #APP
-; SKX-NEXT: salc
+; SKX-NEXT: salc # sched: [1:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_salc:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: salc
+; BTVER2-NEXT: salc # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_salc:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
-; ZNVER1-NEXT: salc
+; ZNVER1-NEXT: salc # sched: [1:0.25]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "salc", "=r"() nounwind
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