[PATCH] D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I

[Mario Werner via Phabricator via llvm-commits]

niosHD created this revision.
Herald added subscribers: jordy.potman.lists, simoncook, johnrusso, rbar.

Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Since the RV64I instructions are not upstream yet the respective
code has been commented out and the tests are marked as XFAIL.


https://reviews.llvm.org/D40902

Files:
  lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
  lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/rv32i-aliases-invalid.s
  test/MC/RISCV/rv32i-aliases-valid.s
  test/MC/RISCV/rv64i-aliases-invalid.s
  test/MC/RISCV/rv64i-aliases-valid.s
  test/MC/RISCV/rvi-aliases-valid.s

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