[llvm] r319887 - [X86][AVX512] Tag Mask<->Vector instructions scheduler classes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Dec  6 03:59:05 2017
New Revision: 319887

URL: http://llvm.org/viewvc/llvm-project?rev=319887&view=rev
Log:
[X86][AVX512] Tag Mask<->Vector instructions scheduler classes

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319887&r1=319886&r2=319887&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Wed Dec  6 03:59:05 2017
@@ -8676,7 +8676,8 @@ defm VSCATTERPF1QPD: avx512_gather_scatt
 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
                   !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
-                  [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
+                  [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))],
+                  IIC_SSE_MOV_S_RR>, EVEX, Sched<[WriteMove]>;
 }
 
 // Use 512bit version to implement 128/256 bit in case NoVLX.
@@ -8714,7 +8715,8 @@ defm VPMOVM2Q : cvt_mask_by_elt_width<0x
 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
     def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
                         !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                        [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
+                        [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))],
+                        IIC_SSE_MOV_S_RR>, EVEX, Sched<[WriteMove]>;
 }
 
 // Use 512bit version to implement 128/256 bit in case NoVLX.