[llvm] r319712 - AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
Jan Vesely via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 4 15:07:28 PST 2017
Author: jvesely
Date: Mon Dec 4 15:07:28 2017
New Revision: 319712
URL: http://llvm.org/viewvc/llvm-project?rev=319712&view=rev
Log:
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
Only used by pre-GCN targets
v2: fix predicate setting for FMA_Common
Differential Revision: https://reviews.llvm.org/D40692
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/R600Instructions.td
llvm/trunk/lib/Target/AMDGPU/R600Processors.td
llvm/trunk/test/CodeGen/AMDGPU/fma.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Mon Dec 4 15:07:28 2017
@@ -19,6 +19,12 @@ def FeatureFP64 : SubtargetFeature<"fp64
"Enable double precision operations"
>;
+def FeatureFMA : SubtargetFeature<"fmaf",
+ "FMA",
+ "true",
+ "Enable single precision FMA (not as fast as mul+add, but fused)"
+>;
+
def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
"FastFMAF32",
"true",
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Mon Dec 4 15:07:28 2017
@@ -49,6 +49,7 @@ def NoFP16Denormals : Predicate<"!Subtar
def NoFP32Denormals : Predicate<"!Subtarget->hasFP32Denormals()">;
def NoFP64Denormals : Predicate<"!Subtarget->hasFP64Denormals()">;
def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
+def FMA : Predicate<"Subtarget->hasFMA()">;
def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Mon Dec 4 15:07:28 2017
@@ -140,6 +140,7 @@ protected:
// Subtarget statically properties set by tablegen
bool FP64;
+ bool FMA;
bool IsGCN;
bool GCN3Encoding;
bool CIInsts;
@@ -348,6 +349,10 @@ public:
return CaymanISA;
}
+ bool hasFMA() const {
+ return FMA;
+ }
+
TrapHandlerAbi getTrapHandlerAbi() const {
return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
}
Modified: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp Mon Dec 4 15:07:28 2017
@@ -211,6 +211,11 @@ R600TargetLowering::R600TargetLowering(c
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ if (!Subtarget->hasFMA()) {
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ }
+
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
Modified: llvm/trunk/lib/Target/AMDGPU/R600Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600Instructions.td?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600Instructions.td Mon Dec 4 15:07:28 2017
@@ -989,7 +989,10 @@ class MULADD_IEEE_Common <bits<5> inst>
class FMA_Common <bits<5> inst> : R600_3OP <
inst, "FMA",
[(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
->;
+>
+{
+ let OtherPredicates = [FMA];
+}
class CNDE_Common <bits<5> inst> : R600_3OP <
inst, "CNDE",
Modified: llvm/trunk/lib/Target/AMDGPU/R600Processors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600Processors.td?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600Processors.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600Processors.td Mon Dec 4 15:07:28 2017
@@ -53,7 +53,7 @@ def : Processor<"cedar", R600_VLIW5_Itin
>;
def : Processor<"cypress", R600_VLIW5_Itin,
- [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
+ [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA]
>;
def : Processor<"juniper", R600_VLIW5_Itin,
@@ -82,7 +82,7 @@ def : Processor<"caicos", R600_VLIW5_Iti
>;
def : Processor<"cayman", R600_VLIW4_Itin,
- [FeatureNorthernIslands, FeatureCaymanISA]
+ [FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA]
>;
def : Processor<"turks", R600_VLIW5_Itin,
Modified: llvm/trunk/test/CodeGen/AMDGPU/fma.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fma.ll?rev=319712&r1=319711&r2=319712&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fma.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fma.ll Mon Dec 4 15:07:28 2017
@@ -1,5 +1,12 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cedar -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=juniper -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=sumo -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=barts -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=caicos -verify-machineinstrs < %s
+; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=turks -verify-machineinstrs < %s
declare float @llvm.fma.f32(float, float, float) nounwind readnone
declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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