[llvm] r319636 - [X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 3 13:16:12 PST 2017
Author: rksimon
Date: Sun Dec 3 13:16:12 2017
New Revision: 319636
URL: http://llvm.org/viewvc/llvm-project?rev=319636&view=rev
Log:
[X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-bugfix-23634.ll
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319636&r1=319635&r2=319636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Dec 3 13:16:12 2017
@@ -6723,74 +6723,81 @@ def : Pat<(v2f64 (X86Movsd
//===----------------------------------------------------------------------===//
multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
- X86VectorVTInfo _Src, SDNode OpNode,
+ X86VectorVTInfo _Src, SDNode OpNode, OpndItins itins,
string Broadcast = _.BroadcastStr,
string Alias = "", X86MemOperand MemOp = _Src.MemOp> {
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _Src.RC:$src), OpcodeStr, "$src", "$src",
- (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
+ (_.VT (OpNode (_Src.VT _Src.RC:$src))), itins.rr>,
+ EVEX, Sched<[itins.Sched]>;
defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins MemOp:$src), OpcodeStr#Alias, "$src", "$src",
(_.VT (OpNode (_Src.VT
- (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
+ (bitconvert (_Src.LdFrag addr:$src))))), itins.rm>,
+ EVEX, Sched<[itins.Sched.Folded]>;
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _Src.ScalarMemOp:$src), OpcodeStr,
"${src}"##Broadcast, "${src}"##Broadcast,
(_.VT (OpNode (_Src.VT
(X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
- ))>, EVEX, EVEX_B;
+ )), itins.rm>, EVEX, EVEX_B,
+ Sched<[itins.Sched.Folded]>;
}
// Coversion with SAE - suppress all exceptions
multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
- X86VectorVTInfo _Src, SDNode OpNodeRnd> {
+ X86VectorVTInfo _Src, SDNode OpNodeRnd,
+ OpndItins itins> {
defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _Src.RC:$src), OpcodeStr,
"{sae}, $src", "$src, {sae}",
(_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
- (i32 FROUND_NO_EXC)))>,
- EVEX, EVEX_B;
+ (i32 FROUND_NO_EXC))), itins.rr>,
+ EVEX, EVEX_B, Sched<[itins.Sched]>;
}
// Conversion with rounding control (RC)
multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
- X86VectorVTInfo _Src, SDNode OpNodeRnd> {
+ X86VectorVTInfo _Src, SDNode OpNodeRnd,
+ OpndItins itins> {
defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
"$rc, $src", "$src, $rc",
- (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
- EVEX, EVEX_B, EVEX_RC;
+ (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc))),
+ itins.rr>, EVEX, EVEX_B, EVEX_RC, Sched<[itins.Sched]>;
}
// Extend Float to Double
-multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
+multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr,
+ OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fpextend>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info,
+ fpextend, itins>,
avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
- X86vfpextRnd>, EVEX_V512;
+ X86vfpextRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
- X86vfpext, "{1to2}", "", f64mem>, EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend>,
- EVEX_V256;
+ X86vfpext, itins, "{1to2}", "", f64mem>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend,
+ itins>, EVEX_V256;
}
}
// Truncate Double to Float
-multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
+multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround, itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
- X86vfproundRnd>, EVEX_V512;
+ X86vfproundRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
- X86vfpround, "{1to2}", "{x}">, EVEX_V128;
+ X86vfpround, itins, "{1to2}", "{x}">, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
- "{1to4}", "{y}">, EVEX_V256;
+ itins, "{1to4}", "{y}">, EVEX_V256;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
@@ -6803,9 +6810,9 @@ multiclass avx512_cvtpd2ps<bits<8> opc,
}
}
-defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
+defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SSE_CVT_PD2PS>,
VEX_W, PD, EVEX_CD8<64, CD8VF>;
-defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
+defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SSE_CVT_PS2PD>,
PS, EVEX_CD8<32, CD8VH>;
def : Pat<(v8f64 (extloadv8f32 addr:$src)),
@@ -6828,75 +6835,80 @@ let Predicates = [HasVLX] in {
// Convert Signed/Unsigned Doubleword to Double
multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
- SDNode OpNode128> {
+ SDNode OpNode128, OpndItins itins> {
// No rounding in this op
let Predicates = [HasAVX512] in
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
- EVEX_V512;
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode,
+ itins>, EVEX_V512;
let Predicates = [HasVLX] in {
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
- OpNode128, "{1to2}", "", i64mem>, EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
- EVEX_V256;
+ OpNode128, itins, "{1to2}", "", i64mem>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Signed/Unsigned Doubleword to Float
multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
- SDNode OpNodeRnd> {
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasAVX512] in
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
let Predicates = [HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Float to Signed/Unsigned Doubleword with truncation
-multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode,
+ itins>,
avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Float to Signed/Unsigned Doubleword
-multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Double to Signed/Unsigned Doubleword with truncation
multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
- SDNode OpNode128, SDNode OpNodeRnd> {
+ SDNode OpNode128, SDNode OpNodeRnd,
+ OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode,
+ itins>,
avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
// we need "x"/"y" suffixes in order to distinguish between 128 and 256
@@ -6904,9 +6916,9 @@ multiclass avx512_cvttpd2dq<bits<8> opc,
// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
// due to the same reason.
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info,
- OpNode128, "{1to2}", "{x}">, EVEX_V128;
+ OpNode128, itins, "{1to2}", "{x}">, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
- "{1to4}", "{y}">, EVEX_V256;
+ itins, "{1to4}", "{y}">, EVEX_V256;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
@@ -6920,12 +6932,13 @@ multiclass avx512_cvttpd2dq<bits<8> opc,
}
// Convert Double to Signed/Unsigned Doubleword
-multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasAVX512] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasVLX] in {
// we need "x"/"y" suffixes in order to distinguish between 128 and 256
@@ -6933,9 +6946,9 @@ multiclass avx512_cvtpd2dq<bits<8> opc,
// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
// due to the same reason.
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
- "{1to2}", "{x}">, EVEX_V128;
+ itins, "{1to2}", "{x}">, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
- "{1to4}", "{y}">, EVEX_V256;
+ itins, "{1to4}", "{y}">, EVEX_V256;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
@@ -6949,96 +6962,102 @@ multiclass avx512_cvtpd2dq<bits<8> opc,
}
// Convert Double to Signed/Unsigned Quardword
-multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd,itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Double to Signed/Unsigned Quardword with truncation
-multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode,
+ itins>,
avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Signed/Unsigned Quardword to Double
-multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
- defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
- EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
- EVEX_V256;
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode,
+ itins>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Float to Signed/Unsigned Quardword
-multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
- SDNode OpNode, SDNode OpNodeRnd> {
+multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
// Explicitly specified broadcast string, since we take only 2 elements
// from v4f32x_info source
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
- "{1to2}", "", f64mem>, EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
- EVEX_V256;
+ itins, "{1to2}", "", f64mem>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Float to Signed/Unsigned Quardword with truncation
multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
- SDNode OpNode128, SDNode OpNodeRnd> {
+ SDNode OpNode128, SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode,
+ itins>,
avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
// Explicitly specified broadcast string, since we take only 2 elements
// from v4f32x_info source
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode128,
- "{1to2}", "", f64mem>, EVEX_V128;
- defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
- EVEX_V256;
+ itins, "{1to2}", "", f64mem>, EVEX_V128;
+ defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode,
+ itins>, EVEX_V256;
}
}
// Convert Signed/Unsigned Quardword to Float
multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
- SDNode OpNode128, SDNode OpNodeRnd> {
+ SDNode OpNode128, SDNode OpNodeRnd, OpndItins itins> {
let Predicates = [HasDQI] in {
- defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
+ defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode,
+ itins>,
avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
- OpNodeRnd>, EVEX_V512;
+ OpNodeRnd, itins>, EVEX_V512;
}
let Predicates = [HasDQI, HasVLX] in {
// we need "x"/"y" suffixes in order to distinguish between 128 and 256
@@ -7046,9 +7065,9 @@ multiclass avx512_cvtqq2ps<bits<8> opc,
// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
// due to the same reason.
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode128,
- "{1to2}", "{x}">, EVEX_V128;
+ itins, "{1to2}", "{x}">, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
- "{1to4}", "{y}">, EVEX_V256;
+ itins, "{1to4}", "{y}">, EVEX_V256;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
@@ -7061,89 +7080,100 @@ multiclass avx512_cvtqq2ps<bits<8> opc,
}
}
-defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP>,
- XS, EVEX_CD8<32, CD8VH>;
+defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP,
+ SSE_CVT_I2PD>, XS, EVEX_CD8<32, CD8VH>;
defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
- X86VSintToFpRnd>,
+ X86VSintToFpRnd, SSE_CVT_I2PS>,
PS, EVEX_CD8<32, CD8VF>;
defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
- X86cvttp2siRnd>,
+ X86cvttp2siRnd, SSE_CVT_PS2I>,
XS, EVEX_CD8<32, CD8VF>;
defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint, X86cvttp2si,
- X86cvttp2siRnd>,
+ X86cvttp2siRnd, SSE_CVT_PD2I>,
PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
- X86cvttp2uiRnd>, PS,
+ X86cvttp2uiRnd, SSE_CVT_PS2I>, PS,
EVEX_CD8<32, CD8VF>;
defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
- X86cvttp2ui, X86cvttp2uiRnd>, PS, VEX_W,
- EVEX_CD8<64, CD8VF>;
+ X86cvttp2ui, X86cvttp2uiRnd, SSE_CVT_PD2I>,
+ PS, VEX_W, EVEX_CD8<64, CD8VF>;
-defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86VUintToFP>,
- XS, EVEX_CD8<32, CD8VH>;
+defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp,
+ X86VUintToFP, SSE_CVT_I2PD>, XS,
+ EVEX_CD8<32, CD8VH>;
defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
- X86VUintToFpRnd>, XD,
+ X86VUintToFpRnd, SSE_CVT_I2PS>, XD,
EVEX_CD8<32, CD8VF>;
defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int,
- X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
+ X86cvtp2IntRnd, SSE_CVT_PS2I>, PD,
+ EVEX_CD8<32, CD8VF>;
defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int,
- X86cvtp2IntRnd>, XD, VEX_W,
- EVEX_CD8<64, CD8VF>;
+ X86cvtp2IntRnd, SSE_CVT_PD2I>, XD,
+ VEX_W, EVEX_CD8<64, CD8VF>;
defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt,
- X86cvtp2UIntRnd>,
+ X86cvtp2UIntRnd, SSE_CVT_PS2I>,
PS, EVEX_CD8<32, CD8VF>;
+
defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt,
- X86cvtp2UIntRnd>, VEX_W,
+ X86cvtp2UIntRnd, SSE_CVT_PD2I>, VEX_W,
PS, EVEX_CD8<64, CD8VF>;
defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int,
- X86cvtp2IntRnd>, VEX_W,
+ X86cvtp2IntRnd, SSE_CVT_PD2I>, VEX_W,
PD, EVEX_CD8<64, CD8VF>;
defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int,
- X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
+ X86cvtp2IntRnd, SSE_CVT_PS2I>, PD,
+ EVEX_CD8<32, CD8VH>;
defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt,
- X86cvtp2UIntRnd>, VEX_W,
+ X86cvtp2UIntRnd, SSE_CVT_PD2I>, VEX_W,
PD, EVEX_CD8<64, CD8VF>;
defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt,
- X86cvtp2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
+ X86cvtp2UIntRnd, SSE_CVT_PS2I>, PD,
+ EVEX_CD8<32, CD8VH>;
defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
- X86cvttp2siRnd>, VEX_W,
+ X86cvttp2siRnd, SSE_CVT_PD2I>, VEX_W,
PD, EVEX_CD8<64, CD8VF>;
defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint, X86cvttp2si,
- X86cvttp2siRnd>, PD, EVEX_CD8<32, CD8VH>;
+ X86cvttp2siRnd, SSE_CVT_PS2I>, PD,
+ EVEX_CD8<32, CD8VH>;
defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
- X86cvttp2uiRnd>, VEX_W,
+ X86cvttp2uiRnd, SSE_CVT_PD2I>, VEX_W,
PD, EVEX_CD8<64, CD8VF>;
defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint, X86cvttp2ui,
- X86cvttp2uiRnd>, PD, EVEX_CD8<32, CD8VH>;
+ X86cvttp2uiRnd, SSE_CVT_PS2I>, PD,
+ EVEX_CD8<32, CD8VH>;
defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
- X86VSintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
+ X86VSintToFpRnd, SSE_CVT_I2PD>, VEX_W, XS,
+ EVEX_CD8<64, CD8VF>;
defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
- X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
+ X86VUintToFpRnd, SSE_CVT_I2PD>, VEX_W, XS,
+ EVEX_CD8<64, CD8VF>;
defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP,
- X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
+ X86VSintToFpRnd, SSE_CVT_I2PS>, VEX_W, PS,
+ EVEX_CD8<64, CD8VF>;
defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP,
- X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
+ X86VUintToFpRnd, SSE_CVT_I2PS>, VEX_W, XD,
+ EVEX_CD8<64, CD8VF>;
let Predicates = [HasAVX512, NoVLX] in {
def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
Modified: llvm/trunk/test/CodeGen/X86/avx512-bugfix-23634.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-bugfix-23634.ll?rev=319636&r1=319635&r2=319636&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-bugfix-23634.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-bugfix-23634.ll Sun Dec 3 13:16:12 2017
@@ -16,8 +16,8 @@ define void @f_fu(float* %ret, float* %
; CHECK-NEXT: movw $-21846, %ax ## imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa32 {{.*}}(%rip), %zmm1 {%k1}
-; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm0, %zmm2, %zmm0
+; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vcvtdq2ps %zmm0, %zmm0
; CHECK-NEXT: vmovups %zmm0, (%rdi)
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=319636&r1=319635&r2=319636&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Sun Dec 3 13:16:12 2017
@@ -1375,7 +1375,7 @@ if.end.i:
define <16 x float> @sitof32(<16 x i32> %a) nounwind {
; GENERIC-LABEL: sitof32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sitof32:
@@ -1389,7 +1389,7 @@ define <16 x float> @sitof32(<16 x i32>
define <8 x double> @sltof864(<8 x i64> %a) {
; GENERIC-LABEL: sltof864:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0
+; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sltof864:
@@ -1403,7 +1403,7 @@ define <8 x double> @sltof864(<8 x i64>
define <4 x double> @slto4f64(<4 x i64> %a) {
; GENERIC-LABEL: slto4f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2pd %ymm0, %ymm0
+; GENERIC-NEXT: vcvtqq2pd %ymm0, %ymm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto4f64:
@@ -1417,7 +1417,7 @@ define <4 x double> @slto4f64(<4 x i64>
define <2 x double> @slto2f64(<2 x i64> %a) {
; GENERIC-LABEL: slto2f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0
+; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto2f64:
@@ -1431,7 +1431,7 @@ define <2 x double> @slto2f64(<2 x i64>
define <2 x float> @sltof2f32(<2 x i64> %a) {
; GENERIC-LABEL: sltof2f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2ps %xmm0, %xmm0
+; GENERIC-NEXT: vcvtqq2ps %xmm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sltof2f32:
@@ -1445,12 +1445,12 @@ define <2 x float> @sltof2f32(<2 x i64>
define <4 x float> @slto4f32_mem(<4 x i64>* %a) {
; GENERIC-LABEL: slto4f32_mem:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2psy (%rdi), %xmm0
+; GENERIC-NEXT: vcvtqq2psy (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto4f32_mem:
; SKX: # BB#0:
-; SKX-NEXT: vcvtqq2psy (%rdi), %xmm0
+; SKX-NEXT: vcvtqq2psy (%rdi), %xmm0 # sched: [9:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%a1 = load <4 x i64>, <4 x i64>* %a, align 8
%b = sitofp <4 x i64> %a1 to <4 x float>
@@ -1460,7 +1460,7 @@ define <4 x float> @slto4f32_mem(<4 x i6
define <4 x i64> @f64to4sl(<4 x double> %a) {
; GENERIC-LABEL: f64to4sl:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2qq %ymm0, %ymm0
+; GENERIC-NEXT: vcvttpd2qq %ymm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f64to4sl:
@@ -1474,7 +1474,7 @@ define <4 x i64> @f64to4sl(<4 x double>
define <4 x i64> @f32to4sl(<4 x float> %a) {
; GENERIC-LABEL: f32to4sl:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2qq %xmm0, %ymm0
+; GENERIC-NEXT: vcvttps2qq %xmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to4sl:
@@ -1488,7 +1488,7 @@ define <4 x i64> @f32to4sl(<4 x float> %
define <4 x float> @slto4f32(<4 x i64> %a) {
; GENERIC-LABEL: slto4f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2ps %ymm0, %xmm0
+; GENERIC-NEXT: vcvtqq2ps %ymm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1504,7 +1504,7 @@ define <4 x float> @slto4f32(<4 x i64> %
define <4 x float> @ulto4f32(<4 x i64> %a) {
; GENERIC-LABEL: ulto4f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtuqq2ps %ymm0, %xmm0
+; GENERIC-NEXT: vcvtuqq2ps %ymm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1520,7 +1520,7 @@ define <4 x float> @ulto4f32(<4 x i64> %
define <8 x double> @ulto8f64(<8 x i64> %a) {
; GENERIC-LABEL: ulto8f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtuqq2pd %zmm0, %zmm0
+; GENERIC-NEXT: vcvtuqq2pd %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ulto8f64:
@@ -1534,8 +1534,8 @@ define <8 x double> @ulto8f64(<8 x i64>
define <16 x double> @ulto16f64(<16 x i64> %a) {
; GENERIC-LABEL: ulto16f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtuqq2pd %zmm0, %zmm0
-; GENERIC-NEXT: vcvtuqq2pd %zmm1, %zmm1
+; GENERIC-NEXT: vcvtuqq2pd %zmm0, %zmm0 # sched: [4:1.00]
+; GENERIC-NEXT: vcvtuqq2pd %zmm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ulto16f64:
@@ -1550,7 +1550,7 @@ define <16 x double> @ulto16f64(<16 x i6
define <16 x i32> @f64to16si(<16 x float> %a) nounwind {
; GENERIC-LABEL: f64to16si:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0
+; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f64to16si:
@@ -1564,7 +1564,7 @@ define <16 x i32> @f64to16si(<16 x float
define <16 x i32> @f32to16ui(<16 x float> %a) nounwind {
; GENERIC-LABEL: f32to16ui:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2udq %zmm0, %zmm0
+; GENERIC-NEXT: vcvttps2udq %zmm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to16ui:
@@ -1578,7 +1578,7 @@ define <16 x i32> @f32to16ui(<16 x float
define <16 x i8> @f32to16uc(<16 x float> %f) {
; GENERIC-LABEL: f32to16uc:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0
+; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovdb %zmm0, %xmm0
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
@@ -1596,7 +1596,7 @@ define <16 x i8> @f32to16uc(<16 x float>
define <16 x i16> @f32to16us(<16 x float> %f) {
; GENERIC-LABEL: f32to16us:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0
+; GENERIC-NEXT: vcvttps2dq %zmm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovdw %zmm0, %ymm0
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1612,7 +1612,7 @@ define <16 x i16> @f32to16us(<16 x float
define <8 x i32> @f32to8ui(<8 x float> %a) nounwind {
; GENERIC-LABEL: f32to8ui:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2udq %ymm0, %ymm0
+; GENERIC-NEXT: vcvttps2udq %ymm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to8ui:
@@ -1626,7 +1626,7 @@ define <8 x i32> @f32to8ui(<8 x float> %
define <4 x i32> @f32to4ui(<4 x float> %a) nounwind {
; GENERIC-LABEL: f32to4ui:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttps2udq %xmm0, %xmm0
+; GENERIC-NEXT: vcvttps2udq %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to4ui:
@@ -1640,7 +1640,7 @@ define <4 x i32> @f32to4ui(<4 x float> %
define <8 x i32> @f64to8ui(<8 x double> %a) nounwind {
; GENERIC-LABEL: f64to8ui:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2udq %zmm0, %ymm0
+; GENERIC-NEXT: vcvttpd2udq %zmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f64to8ui:
@@ -1654,7 +1654,7 @@ define <8 x i32> @f64to8ui(<8 x double>
define <8 x i16> @f64to8us(<8 x double> %f) {
; GENERIC-LABEL: f64to8us:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0
+; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovdw %ymm0, %xmm0
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
@@ -1672,7 +1672,7 @@ define <8 x i16> @f64to8us(<8 x double>
define <8 x i8> @f64to8uc(<8 x double> %f) {
; GENERIC-LABEL: f64to8uc:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0
+; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovdw %ymm0, %xmm0
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
@@ -1690,7 +1690,7 @@ define <8 x i8> @f64to8uc(<8 x double> %
define <4 x i32> @f64to4ui(<4 x double> %a) nounwind {
; GENERIC-LABEL: f64to4ui:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2udq %ymm0, %xmm0
+; GENERIC-NEXT: vcvttpd2udq %ymm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1706,7 +1706,7 @@ define <4 x i32> @f64to4ui(<4 x double>
define <8 x double> @sito8f64(<8 x i32> %a) {
; GENERIC-LABEL: sito8f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sito8f64:
@@ -1720,7 +1720,7 @@ define <8 x double> @i32to8f64_mask(<8 x
; GENERIC-LABEL: i32to8f64_mask:
; GENERIC: # BB#0:
; GENERIC-NEXT: kmovd %edi, %k1
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1}
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: i32to8f64_mask:
@@ -1742,7 +1742,7 @@ define <8 x double> @sito8f64_maskz(<8 x
; GENERIC-LABEL: sito8f64_maskz:
; GENERIC: # BB#0:
; GENERIC-NEXT: kmovd %edi, %k1
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z}
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sito8f64_maskz:
@@ -1764,7 +1764,7 @@ define <8 x double> @sito8f64_maskz(<8 x
define <8 x i32> @f64to8si(<8 x double> %a) {
; GENERIC-LABEL: f64to8si:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0
+; GENERIC-NEXT: vcvttpd2dq %zmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f64to8si:
@@ -1794,8 +1794,8 @@ define <4 x i32> @f64to4si(<4 x double>
define <16 x float> @f64to16f32(<16 x double> %b) nounwind {
; GENERIC-LABEL: f64to16f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtpd2ps %zmm0, %ymm0
-; GENERIC-NEXT: vcvtpd2ps %zmm1, %ymm1
+; GENERIC-NEXT: vcvtpd2ps %zmm0, %ymm0 # sched: [3:1.00]
+; GENERIC-NEXT: vcvtpd2ps %zmm1, %ymm1 # sched: [3:1.00]
; GENERIC-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1830,7 +1830,7 @@ define <4 x float> @f64to4f32_mask(<4 x
; GENERIC: # BB#0:
; GENERIC-NEXT: vpslld $31, %xmm1, %xmm1 # sched: [1:1.00]
; GENERIC-NEXT: vptestmd %xmm1, %xmm1, %k1 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtpd2ps %ymm0, %xmm0 {%k1} {z}
+; GENERIC-NEXT: vcvtpd2ps %ymm0, %xmm0 {%k1} {z} # sched: [3:1.00]
; GENERIC-NEXT: vzeroupper
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -1865,7 +1865,7 @@ define <4 x float> @f64tof32_inreg(<2 x
define <8 x double> @f32to8f64(<8 x float> %b) nounwind {
; GENERIC-LABEL: f32to8f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtps2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtps2pd %ymm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to8f64:
@@ -1880,7 +1880,7 @@ define <4 x double> @f32to4f64_mask(<4 x
; GENERIC-LABEL: f32to4f64_mask:
; GENERIC: # BB#0:
; GENERIC-NEXT: vcmpltpd %ymm2, %ymm1, %k1 # sched: [3:1.00]
-; GENERIC-NEXT: vcvtps2pd %xmm0, %ymm0 {%k1} {z}
+; GENERIC-NEXT: vcvtps2pd %xmm0, %ymm0 {%k1} {z} # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32to4f64_mask:
@@ -2079,9 +2079,9 @@ define i32 @float_to_int(float %x) {
define <16 x double> @uito16f64(<16 x i32> %a) nounwind {
; GENERIC-LABEL: uito16f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm2
+; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm2 # sched: [4:1.00]
; GENERIC-NEXT: vextractf64x4 $1, %zmm0, %ymm0 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm1
+; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: vmovaps %zmm2, %zmm0
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2099,7 +2099,7 @@ define <16 x double> @uito16f64(<16 x i3
define <8 x float> @slto8f32(<8 x i64> %a) {
; GENERIC-LABEL: slto8f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2ps %zmm0, %ymm0
+; GENERIC-NEXT: vcvtqq2ps %zmm0, %ymm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto8f32:
@@ -2113,8 +2113,8 @@ define <8 x float> @slto8f32(<8 x i64> %
define <16 x float> @slto16f32(<16 x i64> %a) {
; GENERIC-LABEL: slto16f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2ps %zmm0, %ymm0
-; GENERIC-NEXT: vcvtqq2ps %zmm1, %ymm1
+; GENERIC-NEXT: vcvtqq2ps %zmm0, %ymm0 # sched: [4:1.00]
+; GENERIC-NEXT: vcvtqq2ps %zmm1, %ymm1 # sched: [4:1.00]
; GENERIC-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2131,7 +2131,7 @@ define <16 x float> @slto16f32(<16 x i64
define <8 x double> @slto8f64(<8 x i64> %a) {
; GENERIC-LABEL: slto8f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0
+; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto8f64:
@@ -2145,8 +2145,8 @@ define <8 x double> @slto8f64(<8 x i64>
define <16 x double> @slto16f64(<16 x i64> %a) {
; GENERIC-LABEL: slto16f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0
-; GENERIC-NEXT: vcvtqq2pd %zmm1, %zmm1
+; GENERIC-NEXT: vcvtqq2pd %zmm0, %zmm0 # sched: [4:1.00]
+; GENERIC-NEXT: vcvtqq2pd %zmm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: slto16f64:
@@ -2161,7 +2161,7 @@ define <16 x double> @slto16f64(<16 x i6
define <8 x float> @ulto8f32(<8 x i64> %a) {
; GENERIC-LABEL: ulto8f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtuqq2ps %zmm0, %ymm0
+; GENERIC-NEXT: vcvtuqq2ps %zmm0, %ymm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ulto8f32:
@@ -2175,8 +2175,8 @@ define <8 x float> @ulto8f32(<8 x i64> %
define <16 x float> @ulto16f32(<16 x i64> %a) {
; GENERIC-LABEL: ulto16f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtuqq2ps %zmm0, %ymm0
-; GENERIC-NEXT: vcvtuqq2ps %zmm1, %ymm1
+; GENERIC-NEXT: vcvtuqq2ps %zmm0, %ymm0 # sched: [4:1.00]
+; GENERIC-NEXT: vcvtuqq2ps %zmm1, %ymm1 # sched: [4:1.00]
; GENERIC-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2194,7 +2194,7 @@ define <8 x double> @uito8f64_mask(<8 x
; GENERIC-LABEL: uito8f64_mask:
; GENERIC: # BB#0:
; GENERIC-NEXT: kmovd %edi, %k1
-; GENERIC-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1}
+; GENERIC-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito8f64_mask:
@@ -2216,7 +2216,7 @@ define <8 x double> @uito8f64_maskz(<8 x
; GENERIC-LABEL: uito8f64_maskz:
; GENERIC: # BB#0:
; GENERIC-NEXT: kmovd %edi, %k1
-; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z}
+; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito8f64_maskz:
@@ -2233,7 +2233,7 @@ define <8 x double> @uito8f64_maskz(<8 x
define <4 x double> @uito4f64(<4 x i32> %a) nounwind {
; GENERIC-LABEL: uito4f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2pd %xmm0, %ymm0
+; GENERIC-NEXT: vcvtudq2pd %xmm0, %ymm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito4f64:
@@ -2247,7 +2247,7 @@ define <4 x double> @uito4f64(<4 x i32>
define <16 x float> @uito16f32(<16 x i32> %a) nounwind {
; GENERIC-LABEL: uito16f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtudq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito16f32:
@@ -2261,7 +2261,7 @@ define <16 x float> @uito16f32(<16 x i32
define <8 x double> @uito8f64(<8 x i32> %a) {
; GENERIC-LABEL: uito8f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtudq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito8f64:
@@ -2275,7 +2275,7 @@ define <8 x double> @uito8f64(<8 x i32>
define <8 x float> @uito8f32(<8 x i32> %a) nounwind {
; GENERIC-LABEL: uito8f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2ps %ymm0, %ymm0
+; GENERIC-NEXT: vcvtudq2ps %ymm0, %ymm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito8f32:
@@ -2289,7 +2289,7 @@ define <8 x float> @uito8f32(<8 x i32> %
define <4 x float> @uito4f32(<4 x i32> %a) nounwind {
; GENERIC-LABEL: uito4f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtudq2ps %xmm0, %xmm0
+; GENERIC-NEXT: vcvtudq2ps %xmm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uito4f32:
@@ -2362,7 +2362,7 @@ define <16 x float> @sbto16f32(<16 x i32
; GENERIC-NEXT: vpxor %xmm1, %xmm1, %xmm1 # sched: [1:0.33]
; GENERIC-NEXT: vpcmpgtd %zmm0, %zmm1, %k0
; GENERIC-NEXT: vpmovm2d %k0, %zmm0
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sbto16f32:
@@ -2381,7 +2381,7 @@ define <16 x float> @scto16f32(<16 x i8>
; GENERIC-LABEL: scto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxbd %xmm0, %zmm0
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: scto16f32:
@@ -2397,7 +2397,7 @@ define <16 x float> @ssto16f32(<16 x i16
; GENERIC-LABEL: ssto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxwd %ymm0, %zmm0
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ssto16f32:
@@ -2413,7 +2413,7 @@ define <8 x double> @ssto16f64(<8 x i16>
; GENERIC-LABEL: ssto16f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxwd %xmm0, %ymm0 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ssto16f64:
@@ -2431,7 +2431,7 @@ define <8 x double> @scto8f64(<8 x i8> %
; GENERIC-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [1:1.00]
; GENERIC-NEXT: vpslld $24, %ymm0, %ymm0 # sched: [1:1.00]
; GENERIC-NEXT: vpsrad $24, %ymm0, %ymm0 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: scto8f64:
@@ -2449,9 +2449,9 @@ define <16 x double> @scto16f64(<16 x i8
; GENERIC-LABEL: scto16f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxbd %xmm0, %zmm1
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vextracti64x4 $1, %zmm1, %ymm1 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: scto16f64:
@@ -2472,9 +2472,9 @@ define <16 x double> @sbto16f64(<16 x do
; GENERIC-NEXT: vcmpltpd %zmm1, %zmm2, %k0 # sched: [3:1.00]
; GENERIC-NEXT: vcmpltpd %zmm0, %zmm2, %k1 # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2d %k1, %ymm0
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vpmovm2d %k0, %ymm1
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sbto16f64:
@@ -2498,7 +2498,7 @@ define <8 x double> @sbto8f64(<8 x doubl
; GENERIC-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # sched: [1:1.00]
; GENERIC-NEXT: vcmpltpd %zmm0, %zmm1, %k0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2d %k0, %ymm0
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sbto8f64:
@@ -2603,7 +2603,7 @@ define <2 x double> @sbto2f64(<2 x doubl
; GENERIC-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # sched: [1:1.00]
; GENERIC-NEXT: vcmpltpd %xmm0, %xmm1, %k0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2q %k0, %xmm0
-; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0
+; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sbto2f64:
@@ -2622,7 +2622,7 @@ define <16 x float> @ucto16f32(<16 x i8>
; GENERIC-LABEL: ucto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ucto16f32:
@@ -2639,7 +2639,7 @@ define <8 x double> @ucto8f64(<8 x i8> %
; GENERIC: # BB#0:
; GENERIC-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 # sched: [7:0.50]
; GENERIC-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ucto8f64:
@@ -2656,7 +2656,7 @@ define <16 x float> @swto16f32(<16 x i16
; GENERIC-LABEL: swto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxwd %ymm0, %zmm0
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: swto16f32:
@@ -2672,7 +2672,7 @@ define <8 x double> @swto8f64(<8 x i16>
; GENERIC-LABEL: swto8f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxwd %xmm0, %ymm0 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: swto8f64:
@@ -2688,9 +2688,9 @@ define <16 x double> @swto16f64(<16 x i1
; GENERIC-LABEL: swto16f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovsxwd %ymm0, %zmm1
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vextracti64x4 $1, %zmm1, %ymm1 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: swto16f64:
@@ -2708,9 +2708,9 @@ define <16 x double> @ucto16f64(<16 x i8
; GENERIC-LABEL: ucto16f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vextracti64x4 $1, %zmm1, %ymm1 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ucto16f64:
@@ -2728,7 +2728,7 @@ define <16 x float> @uwto16f32(<16 x i16
; GENERIC-LABEL: uwto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uwto16f32:
@@ -2744,7 +2744,7 @@ define <8 x double> @uwto8f64(<8 x i16>
; GENERIC-LABEL: uwto8f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uwto8f64:
@@ -2760,9 +2760,9 @@ define <16 x double> @uwto16f64(<16 x i1
; GENERIC-LABEL: uwto16f64:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vextracti64x4 $1, %zmm1, %ymm1 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: uwto16f64:
@@ -2779,7 +2779,7 @@ define <16 x double> @uwto16f64(<16 x i1
define <16 x float> @sito16f32(<16 x i32> %a) {
; GENERIC-LABEL: sito16f32:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sito16f32:
@@ -2793,9 +2793,9 @@ define <16 x float> @sito16f32(<16 x i32
define <16 x double> @sito16f64(<16 x i32> %a) {
; GENERIC-LABEL: sito16f64:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm2
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm2 # sched: [4:1.00]
; GENERIC-NEXT: vextractf64x4 $1, %zmm0, %ymm0 # sched: [1:1.00]
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: vmovaps %zmm2, %zmm0
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2814,7 +2814,7 @@ define <16 x float> @usto16f32(<16 x i16
; GENERIC-LABEL: usto16f32:
; GENERIC: # BB#0:
; GENERIC-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: usto16f32:
@@ -2832,7 +2832,7 @@ define <16 x float> @ubto16f32(<16 x i32
; GENERIC-NEXT: vpxor %xmm1, %xmm1, %xmm1 # sched: [1:0.33]
; GENERIC-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; GENERIC-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
-; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0
+; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ubto16f32:
@@ -2854,10 +2854,10 @@ define <16 x double> @ubto16f64(<16 x i3
; GENERIC-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; GENERIC-NEXT: movl {{.*}}(%rip), %eax # sched: [5:0.50]
; GENERIC-NEXT: vpbroadcastd %eax, %ymm0 {%k1} {z}
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: kshiftrw $8, %k1, %k1
; GENERIC-NEXT: vpbroadcastd %eax, %ymm1 {%k1} {z}
-; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1
+; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ubto16f64:
@@ -2903,7 +2903,7 @@ define <8 x double> @ubto8f64(<8 x i32>
; GENERIC-NEXT: vpxor %xmm1, %xmm1, %xmm1 # sched: [1:0.33]
; GENERIC-NEXT: vpcmpgtd %ymm0, %ymm1, %k1
; GENERIC-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
-; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtdq2pd %ymm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ubto8f64:
@@ -2990,7 +2990,7 @@ define <2 x double> @ubto2f64(<2 x i32>
; GENERIC-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] sched: [1:0.50]
; GENERIC-NEXT: vpcmpltuq %xmm1, %xmm0, %k1
; GENERIC-NEXT: vmovdqa64 {{.*}}(%rip), %xmm0 {%k1} {z} # sched: [4:0.50]
-; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0
+; GENERIC-NEXT: vcvtqq2pd %xmm0, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: ubto2f64:
@@ -4270,7 +4270,7 @@ define <8 x i64> @zext_8x32_to_8x64mask(
define <8 x float> @fptrunc_test(<8 x double> %a) nounwind readnone {
; GENERIC-LABEL: fptrunc_test:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtpd2ps %zmm0, %ymm0
+; GENERIC-NEXT: vcvtpd2ps %zmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: fptrunc_test:
@@ -4284,7 +4284,7 @@ define <8 x float> @fptrunc_test(<8 x do
define <8 x double> @fpext_test(<8 x float> %a) nounwind readnone {
; GENERIC-LABEL: fpext_test:
; GENERIC: # BB#0:
-; GENERIC-NEXT: vcvtps2pd %ymm0, %zmm0
+; GENERIC-NEXT: vcvtps2pd %ymm0, %zmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: fpext_test:
More information about the llvm-commits
mailing list