[llvm] r319465 - [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Thu Nov 30 12:06:02 2017
New Revision: 319465

URL: http://llvm.org/viewvc/llvm-project?rev=319465&view=rev
Log:
[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.

This fixes PR35358.

rdar://35619533

Differential Revision: https://reviews.llvm.org/D40604

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=319465&r1=319464&r2=319465&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Nov 30 12:06:02 2017
@@ -238,6 +238,8 @@ bool IRTranslator::translateCompare(cons
 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
   const ReturnInst &RI = cast<ReturnInst>(U);
   const Value *Ret = RI.getReturnValue();
+  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
+    Ret = nullptr;
   // The target may mess up with the insertion point, but
   // this is not important as a return is the last instruction
   // of the block anyway.
@@ -337,6 +339,9 @@ bool IRTranslator::translateLoad(const U
                                : MachineMemOperand::MONone;
   Flags |= MachineMemOperand::MOLoad;
 
+  if (DL->getTypeStoreSize(LI.getType()) == 0)
+    return true;
+
   unsigned Res = getOrCreateVReg(LI);
   unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
 
@@ -355,6 +360,9 @@ bool IRTranslator::translateStore(const
                                : MachineMemOperand::MONone;
   Flags |= MachineMemOperand::MOStore;
 
+  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
+    return true;
+
   unsigned Val = getOrCreateVReg(*SI.getValueOperand());
   unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
 
@@ -1269,8 +1277,11 @@ bool IRTranslator::runOnMachineFunction(
 
   // Lower the actual args into this basic block.
   SmallVector<unsigned, 8> VRegArgs;
-  for (const Argument &Arg: F.args())
+  for (const Argument &Arg: F.args()) {
+    if (DL->getTypeStoreSize(Arg.getType()) == 0)
+      continue; // Don't handle zero sized types.
     VRegArgs.push_back(getOrCreateVReg(Arg));
+  }
   if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                                MF->getFunction()->getSubprogram(),

Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=319465&r1=319464&r2=319465&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Thu Nov 30 12:06:02 2017
@@ -259,6 +259,8 @@ bool AArch64CallLowering::lowerFormalArg
   SmallVector<ArgInfo, 8> SplitArgs;
   unsigned i = 0;
   for (auto &Arg : F.args()) {
+    if (DL.getTypeStoreSize(Arg.getType()) == 0)
+      continue;
     ArgInfo OrigArg{VRegs[i], Arg.getType()};
     setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
     bool Split = false;

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=319465&r1=319464&r2=319465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Nov 30 12:06:02 2017
@@ -1636,3 +1636,16 @@ define i32 @test_target_mem_intrinsic(i3
 }
 
 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
+
+%zerosize_type = type {}
+
+define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone {
+; CHECK-LABEL: name: test_empty_load_store
+; CHECK-NOT: G_STORE
+; CHECK-NOT: G_LOAD
+; CHECK: RET_ReallyLR
+entry:
+  store %zerosize_type undef, %zerosize_type* undef, align 4
+  %val = load %zerosize_type, %zerosize_type* %ptr, align 4
+  ret %zerosize_type %in
+}