[PATCH] D40444: [DAGCombine] Handle big endian correctly in CombineConsecutiveLoads

[Nirav Dave via Phabricator via llvm-commits]

niravd added a comment.

Passing a struct of i16 by load to generate a BUILD_PAIR and

> I had a hard time trying to do something like that. I basically need some target that will produce a BUILD_PAIR during ISel, often that happens when having some argument passed byval(?).
>  I found out that I could get the optimization to trigger for PowerPC, but PowerPC is during legalization splitting the combined load into two smaller loads again. That is what happens in test/CodeGen/PowerPC/anon_aggr.ll for one of the RUN-lines. So there is already an in-tree test for which the optimization now triggers, and where the end result ends up the same as before.
> 
> I actually wanted to create a test case that showed that we could get miscompiles earlier, but I haven't been able to do that for any in-tree-target. For that to happen I need SelectionDAG to create a BUILD_PAIR where the two loads are in non-consecutive order. I don't know how to trigger that.

Do they have to be non-consecutive? Could you get something by doing a direct operation on the BUILD_PAIR. Something like load a struct of {i16, i16} , citcast the struct to an i32, apply a (+ 1), and return it. Ideally we could have that case, but I suspect it's not worth the time to spend too much time working something out and a case dumping debug information is reasonable.

In https://reviews.llvm.org/D40444#935979, @bjope wrote:

> In https://reviews.llvm.org/D40444#935956, @niravd wrote:
>
> > I've done a double check myself for all in-tree uses and all the uses of areNonVolatileConsecutiveLoads should be fine as well.
> >
> > So modulo a test case this LGTM.
>
>
> So the existing test/CodeGen/PowerPC/anon_aggr.ll test was not enough?
>
> What kind of test are you requesting? Something that dumps output after ISel to see that we got some load combines?
>  I had a hard time trying to do something like that. I basically need some target that will produce a BUILD_PAIR during ISel, often that happens when having some argument passed byval(?).
>  I found out that I could get the optimization to trigger for PowerPC, but PowerPC is during legalization splitting the combined load into two smaller loads again. That is what happens in test/CodeGen/PowerPC/anon_aggr.ll for one of the RUN-lines. So there is already an in-tree test for which the optimization now triggers, and where the end result ends up the same as before.
>
> I actually wanted to create a test case that showed that we could get miscompiles earlier, but I haven't been able to do that for any in-tree-target. For that to happen I need SelectionDAG to create a BUILD_PAIR where the two loads are in non-consecutive order. I don't know how to trigger that.





https://reviews.llvm.org/D40444