[PATCH] D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection

[Friedman, Eli via llvm-commits]

The example looks like there's a bug in the handling of truncstores: 
DAGCombiner::MergeStoresOfConstantsOrVecElts does "StoreInt |= 
C->getAPIntValue().zextOrTrunc(SizeInBits);", which doesn't correctly 
mask away the extra bits of a truncstore.  Not sure how to write a 
testcase, though.

-Eli

On 11/29/2017 11:01 AM, Nirav Davé wrote:
> Disabled in ARM in r319331.
>
> On Wed, Nov 29, 2017 at 12:31 PM, Nirav Davé <niravd at google.com 
> <mailto:niravd at google.com>> wrote:
>
>     Sure If no one objects I'll disable this for just the ARM target.
>
>     -Nirav
>
>     On Wed, Nov 29, 2017 at 12:23 PM, Evgeny Astigeevich via
>     Phabricator <reviews at reviews.llvm.org
>     <mailto:reviews at reviews.llvm.org>> wrote:
>
>         eastig added a comment.
>
>         Hi Nirav,
>
>         Could you please revert the changes? They affected Arm targets
>         (Thumb2 code).
>         The following sequence of stores:
>
>           MOVS     r0,#0xe5
>           STRB     r0,[r6,#0x1e5]
>           MOVS     r0,#0xe4
>           STRB     r0,[r6,#0x1e4]
>           MOVS     r0,#0xe6
>           STRB     r0,[r6,#0x1e6]
>           MOVS     r0,#0xe7
>           STRB     r0,[r6,#0x1e7]
>
>         is optimised into
>
>           MVN      r0,#0x1b
>           STR      r0,[r6,#0x1e4]
>
>         causing incorrect data to be written.
>
>         We are working on a reproducer.
>
>         Thanks,
>         Evgeny Astigeevich
>         The Arm Compiler Optimisation team
>
>
>         Repository:
>           rL LLVM
>
>         https://reviews.llvm.org/D33675 <https://reviews.llvm.org/D33675>
>
>
>
>
>

-- 
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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