[PATCH] D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection

[Evgeny Astigeevich via Phabricator via llvm-commits]

eastig added a comment.

Hi Nirav,

Could you please revert the changes? They affected Arm targets (Thumb2 code).
The following sequence of stores:

  MOVS     r0,#0xe5
  STRB     r0,[r6,#0x1e5]
  MOVS     r0,#0xe4
  STRB     r0,[r6,#0x1e4]
  MOVS     r0,#0xe6
  STRB     r0,[r6,#0x1e6]
  MOVS     r0,#0xe7
  STRB     r0,[r6,#0x1e7]

is optimised into

  MVN      r0,#0x1b
  STR      r0,[r6,#0x1e4]

causing incorrect data to be written.

We are working on a reproducer.

Thanks,
Evgeny Astigeevich
The Arm Compiler Optimisation team


Repository:
  rL LLVM

https://reviews.llvm.org/D33675