mir-canon simplified patch
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 16:29:42 PST 2017
Puyan Lotfi <puyan.lotfi.llvm at gmail.com> writes:
> This is the test I intend to add in the next week or so.
> It's based on one of the dhrystone source files from the llvm test suite
> (that I used originally to develop the canon pass).
I was thinking more along the lines of a few simpler tests that test the
individual things the canonicalizer is doing, rather than just one big
integration test. Things like a test that just shows renaming vregs on a
simple case with a few instructions, and a test that shows the
rescheduling to move defs close to uses.
A bigger integration test like this one is probably okay too, but if we
add it we should be careful to make sure it's useful without being too
fragile.
> commit 3c28858d57293a6eb57d420f212103e1a3fb73ce
> Author: Puyan Lotfi <plotfi at apple.com>
> Date: Sat Nov 25 01:16:03 2017 -0500
>
> [mir-canon]: Adding a test for mir-canonicalizer pass.
>
> diff --git a/test/CodeGen/MIR/AArch64/mir-canon-dry-sd.mir b/test/CodeGen/MIR/AArch64/mir-canon-dry-sd.mir
> new file mode 100644
> index 00000000000..4f05b84a7de
> --- /dev/null
> +++ b/test/CodeGen/MIR/AArch64/mir-canon-dry-sd.mir
> @@ -0,0 +1,319 @@
> +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
> +
> +# CHECK: STRDui %16373, %stack.6.tmp9
> +# CHECK: STRXui %9387, %9388
> +# CHECK: %w0 = COPY %9389
> +
> +--- |
> + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
> + target triple = "arm64-apple-ios11.0.0"
> +
> + @IntGlob = common global double 0.000000e+00, align 8
> +
> + define i32 @Proc8(double* %arg, [51 x double]* %arg1, double %arg2, double %arg3) #0 {
> + bb:
> + %tmp = alloca i32, align 4
> + %tmp4 = alloca double*, align 8
> + %tmp5 = alloca [51 x double]*, align 8
> + %tmp6 = alloca double, align 8
> + %tmp7 = alloca double, align 8
> + %tmp8 = alloca double, align 8
> + %tmp9 = alloca double, align 8
> + store double* %arg, double** %tmp4, align 8
> + store [51 x double]* %arg1, [51 x double]** %tmp5, align 8
> + store double %arg2, double* %tmp6, align 8
> + store double %arg3, double* %tmp7, align 8
> + %tmp10 = load double, double* %tmp6, align 8
> + %tmp11 = fadd double %tmp10, 5.000000e+00
> + store double %tmp11, double* %tmp8, align 8
> + %tmp12 = load double, double* %tmp7, align 8
> + %tmp13 = load double*, double** %tmp4, align 8
> + %tmp14 = load double, double* %tmp8, align 8
> + %tmp15 = fptosi double %tmp14 to i32
> + %tmp16 = sext i32 %tmp15 to i64
> + %tmp17 = getelementptr inbounds double, double* %tmp13, i64 %tmp16
> + store double %tmp12, double* %tmp17, align 8
> + %tmp18 = load double*, double** %tmp4, align 8
> + %tmp19 = load double, double* %tmp8, align 8
> + %tmp20 = fptosi double %tmp19 to i32
> + %tmp21 = sext i32 %tmp20 to i64
> + %tmp22 = getelementptr inbounds double, double* %tmp18, i64 %tmp21
> + %tmp23 = load double, double* %tmp22, align 8
> + %tmp24 = load double*, double** %tmp4, align 8
> + %tmp25 = load double, double* %tmp8, align 8
> + %tmp26 = fptosi double %tmp25 to i32
> + %tmp27 = add nsw i32 %tmp26, 1
> + %tmp28 = sext i32 %tmp27 to i64
> + %tmp29 = getelementptr inbounds double, double* %tmp24, i64 %tmp28
> + store double %tmp23, double* %tmp29, align 8
> + %tmp30 = load double, double* %tmp8, align 8
> + %tmp31 = load double*, double** %tmp4, align 8
> + %tmp32 = load double, double* %tmp8, align 8
> + %tmp33 = fptosi double %tmp32 to i32
> + %tmp34 = add nsw i32 %tmp33, 30
> + %tmp35 = sext i32 %tmp34 to i64
> + %tmp36 = getelementptr inbounds double, double* %tmp31, i64 %tmp35
> + store double %tmp30, double* %tmp36, align 8
> + %tmp37 = load double, double* %tmp8, align 8
> + store double %tmp37, double* %tmp9, align 8
> + br label %bb38
> +
> + bb38:
> + %tmp39 = load double, double* %tmp9, align 8
> + %tmp40 = load double, double* %tmp8, align 8
> + %tmp41 = fadd double %tmp40, 1.000000e+00
> + %tmp42 = fcmp ole double %tmp39, %tmp41
> + br i1 %tmp42, label %bb43, label %bb57
> +
> + bb43:
> + %tmp44 = load double, double* %tmp8, align 8
> + %tmp45 = load [51 x double]*, [51 x double]** %tmp5, align 8
> + %tmp46 = load double, double* %tmp8, align 8
> + %tmp47 = fptosi double %tmp46 to i32
> + %tmp48 = sext i32 %tmp47 to i64
> + %tmp49 = getelementptr inbounds [51 x double], [51 x double]* %tmp45, i64 %tmp48
> + %tmp50 = load double, double* %tmp9, align 8
> + %tmp51 = fptosi double %tmp50 to i32
> + %tmp52 = sext i32 %tmp51 to i64
> + %tmp53 = getelementptr inbounds [51 x double], [51 x double]* %tmp49, i64 0, i64 %tmp52
> + store double %tmp44, double* %tmp53, align 8
> + %tmp55 = load double, double* %tmp9, align 8
> + %tmp56 = fadd double %tmp55, 1.000000e+00
> + store double %tmp56, double* %tmp9, align 8
> + br label %bb38
> +
> + bb57:
> + %tmp58 = load [51 x double]*, [51 x double]** %tmp5, align 8
> + %tmp59 = load double, double* %tmp8, align 8
> + %tmp60 = fptosi double %tmp59 to i32
> + %tmp61 = sext i32 %tmp60 to i64
> + %tmp62 = getelementptr inbounds [51 x double], [51 x double]* %tmp58, i64 %tmp61
> + %tmp63 = load double, double* %tmp8, align 8
> + %tmp64 = fptosi double %tmp63 to i32
> + %tmp66 = sext i32 %tmp64 to i64
> + %tmp65 = sub nsw i64 %tmp66, 1
> + %tmp67 = getelementptr inbounds [51 x double], [51 x double]* %tmp62, i64 0, i64 %tmp65
> + %tmp68 = load double, double* %tmp67, align 8
> + %tmp69 = fadd double %tmp68, 1.000000e+00
> + store double %tmp69, double* %tmp67, align 8
> + %tmp70 = load double*, double** %tmp4, align 8
> + %tmp71 = load double, double* %tmp8, align 8
> + %tmp72 = fptosi double %tmp71 to i32
> + %tmp73 = sext i32 %tmp72 to i64
> + %tmp74 = getelementptr inbounds double, double* %tmp70, i64 %tmp73
> + %tmp75 = load double, double* %tmp74, align 8
> + %tmp76 = load [51 x double]*, [51 x double]** %tmp5, align 8
> + %tmp77 = load double, double* %tmp8, align 8
> + %tmp78 = fptosi double %tmp77 to i32
> + %tmp79 = add nsw i32 %tmp78, 20
> + %tmp80 = sext i32 %tmp79 to i64
> + %tmp81 = getelementptr inbounds [51 x double], [51 x double]* %tmp76, i64 %tmp80
> + %tmp82 = load double, double* %tmp8, align 8
> + %tmp83 = fptosi double %tmp82 to i32
> + %tmp84 = sext i32 %tmp83 to i64
> + %tmp85 = getelementptr inbounds [51 x double], [51 x double]* %tmp81, i64 0, i64 %tmp84
> + store double %tmp75, double* %tmp85, align 8
> + store double 5.000000e+00, double* @IntGlob, align 8
> + %tmp86 = load i32, i32* %tmp, align 4
> + ret i32 %tmp86
> + }
> +
> + attributes #0 = { noinline nounwind ssp "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+crypto,+neon,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
> +
> +...
> +---
> +name: Proc8
> +alignment: 2
> +exposesReturnsTwice: false
> +legalized: false
> +regBankSelected: false
> +selected: false
> +tracksRegLiveness: true
> +registers:
> + - { id: 0, class: gpr64common, preferred-register: '' }
> + - { id: 1, class: gpr64, preferred-register: '' }
> + - { id: 2, class: fpr64, preferred-register: '' }
> + - { id: 3, class: fpr64, preferred-register: '' }
> + - { id: 4, class: fpr64, preferred-register: '' }
> + - { id: 5, class: fpr64, preferred-register: '' }
> + - { id: 6, class: gpr32, preferred-register: '' }
> + - { id: 7, class: gpr64common, preferred-register: '' }
> + - { id: 8, class: fpr64, preferred-register: '' }
> + - { id: 9, class: gpr32common, preferred-register: '' }
> + - { id: 10, class: fpr64, preferred-register: '' }
> + - { id: 11, class: gpr32common, preferred-register: '' }
> + - { id: 12, class: fpr64, preferred-register: '' }
> + - { id: 13, class: gpr64common, preferred-register: '' }
> + - { id: 14, class: gpr32common, preferred-register: '' }
> + - { id: 15, class: gpr32common, preferred-register: '' }
> + - { id: 16, class: fpr64, preferred-register: '' }
> + - { id: 17, class: fpr64, preferred-register: '' }
> + - { id: 18, class: fpr64, preferred-register: '' }
> + - { id: 19, class: fpr64, preferred-register: '' }
> + - { id: 20, class: fpr64, preferred-register: '' }
> + - { id: 21, class: gpr64, preferred-register: '' }
> + - { id: 22, class: fpr64, preferred-register: '' }
> + - { id: 23, class: gpr32, preferred-register: '' }
> + - { id: 24, class: gpr32, preferred-register: '' }
> + - { id: 25, class: gpr64common, preferred-register: '' }
> + - { id: 26, class: gpr64sp, preferred-register: '' }
> + - { id: 27, class: fpr64, preferred-register: '' }
> + - { id: 28, class: fpr64, preferred-register: '' }
> + - { id: 29, class: fpr64, preferred-register: '' }
> + - { id: 30, class: gpr64common, preferred-register: '' }
> + - { id: 31, class: fpr64, preferred-register: '' }
> + - { id: 32, class: gpr32common, preferred-register: '' }
> + - { id: 33, class: gpr64, preferred-register: '' }
> + - { id: 34, class: gpr64all, preferred-register: '' }
> + - { id: 35, class: gpr64, preferred-register: '' }
> + - { id: 36, class: fpr64, preferred-register: '' }
> + - { id: 37, class: gpr64, preferred-register: '' }
> + - { id: 38, class: gpr32common, preferred-register: '' }
> + - { id: 39, class: gpr64common, preferred-register: '' }
> + - { id: 40, class: gpr64common, preferred-register: '' }
> + - { id: 41, class: gpr64, preferred-register: '' }
> + - { id: 42, class: gpr32, preferred-register: '' }
> + - { id: 43, class: fpr64, preferred-register: '' }
> + - { id: 44, class: gpr64, preferred-register: '' }
> + - { id: 45, class: gpr32, preferred-register: '' }
> + - { id: 46, class: gpr32, preferred-register: '' }
> + - { id: 47, class: gpr64common, preferred-register: '' }
> + - { id: 48, class: fpr64, preferred-register: '' }
> + - { id: 49, class: gpr32, preferred-register: '' }
> + - { id: 50, class: fpr64, preferred-register: '' }
> + - { id: 51, class: fpr64, preferred-register: '' }
> + - { id: 52, class: fpr64, preferred-register: '' }
> +liveins:
> + - { reg: '%x0', virtual-reg: '%0' }
> + - { reg: '%x1', virtual-reg: '%1' }
> + - { reg: '%d0', virtual-reg: '%2' }
> + - { reg: '%d1', virtual-reg: '%3' }
> +frameInfo:
> + isFrameAddressTaken: false
> + isReturnAddressTaken: false
> + hasStackMap: false
> + hasPatchPoint: false
> + stackSize: 0
> + offsetAdjustment: 0
> + maxAlignment: 8
> + adjustsStack: false
> + hasCalls: false
> + stackProtector: ''
> + maxCallFrameSize: 4294967295
> + hasOpaqueSPAdjustment: false
> + hasVAStart: false
> + hasMustTailInVarArgFunc: false
> + savePoint: ''
> + restorePoint: ''
> +fixedStack:
> +stack:
> + - { id: 0, name: tmp, type: default, offset: 0, size: 4, alignment: 4,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -4, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 1, name: tmp4, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -16, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 2, name: tmp5, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -24, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 3, name: tmp6, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -32, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 4, name: tmp7, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -40, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 5, name: tmp8, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -48, di-variable: '', di-expression: '', di-location: '' }
> + - { id: 6, name: tmp9, type: default, offset: 0, size: 8, alignment: 8,
> + stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
> + local-offset: -56, di-variable: '', di-expression: '', di-location: '' }
> +constants:
> +body: |
> + bb.0.bb:
> + successors: %bb.1.bb38(0x80000000)
> + liveins: %x0, %x1, %d0, %d1
> +
> + %3 = COPY %d1
> + %2 = COPY %d0
> + %1 = COPY %x1
> + %0 = COPY %x0
> + STRXui %0, %stack.1.tmp4, 0 :: (store 8 into %ir.tmp4)
> + STRXui %1, %stack.2.tmp5, 0 :: (store 8 into %ir.tmp5)
> + STRDui %2, %stack.3.tmp6, 0 :: (store 8 into %ir.tmp6)
> + STRDui %3, %stack.4.tmp7, 0 :: (store 8 into %ir.tmp7)
> + %4 = FMOVDi 20
> + %5 = FADDDrr %2, killed %4
> + STRDui %5, %stack.5.tmp8, 0 :: (store 8 into %ir.tmp8)
> + %6 = FCVTZSUWDr %5
> + STRDroW %3, %0, killed %6, 1, 1 :: (store 8 into %ir.tmp17)
> + %7 = LDRXui %stack.1.tmp4, 0 :: (dereferenceable load 8 from %ir.tmp4)
> + %8 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %9 = FCVTZSUWDr killed %8
> + %10 = LDRDroW %7, %9, 1, 1 :: (load 8 from %ir.tmp22)
> + %11 = ADDWri %9, 1, 0
> + STRDroW killed %10, %7, killed %11, 1, 1 :: (store 8 into %ir.tmp29)
> + %12 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %13 = LDRXui %stack.1.tmp4, 0 :: (dereferenceable load 8 from %ir.tmp4)
> + %14 = FCVTZSUWDr %12
> + %15 = ADDWri killed %14, 30, 0
> + STRDroW %12, killed %13, killed %15, 1, 1 :: (store 8 into %ir.tmp36)
> + %16 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + STRDui killed %16, %stack.6.tmp9, 0 :: (store 8 into %ir.tmp9)
> + %19 = FMOVDi 112
> + %46 = MOVi32imm 408
> +
> + bb.1.bb38:
> + successors: %bb.2.bb43(0x7c000000), %bb.3.bb57(0x04000000)
> +
> + %17 = LDRDui %stack.6.tmp9, 0 :: (dereferenceable load 8 from %ir.tmp9)
> + %18 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %20 = FADDDrr killed %18, %19
> + FCMPDrr killed %17, killed %20, implicit-def %nzcv
> + Bcc 8, %bb.3.bb57, implicit %nzcv
> + B %bb.2.bb43
> +
> + bb.2.bb43:
> + successors: %bb.1.bb38(0x80000000)
> +
> + %43 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %44 = LDRXui %stack.2.tmp5, 0 :: (dereferenceable load 8 from %ir.tmp5)
> + %45 = FCVTZSUWDr %43
> + %47 = SMADDLrrr killed %45, %46, killed %44
> + %48 = LDRDui %stack.6.tmp9, 0 :: (dereferenceable load 8 from %ir.tmp9)
> + %49 = FCVTZSUWDr killed %48
> + STRDroW %43, killed %47, killed %49, 1, 1 :: (store 8 into %ir.tmp53)
> + %50 = LDRDui %stack.6.tmp9, 0 :: (dereferenceable load 8 from %ir.tmp9)
> + %52 = FADDDrr killed %50, %19
> + STRDui killed %52, %stack.6.tmp9, 0 :: (store 8 into %ir.tmp9)
> + B %bb.1.bb38
> +
> + bb.3.bb57:
> + %21 = LDRXui %stack.2.tmp5, 0 :: (dereferenceable load 8 from %ir.tmp5)
> + %22 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %23 = FCVTZSUWDr killed %22
> + %24 = MOVi32imm 408
> + %25 = SMADDLrrr %23, %24, killed %21
> + %26 = ADDXrx killed %25, %23, 51
> + %27 = LDURDi %26, -8 :: (load 8 from %ir.tmp67)
> + %29 = FADDDrr killed %27, %19
> + STURDi killed %29, %26, -8 :: (store 8 into %ir.tmp67)
> + %30 = LDRXui %stack.1.tmp4, 0 :: (dereferenceable load 8 from %ir.tmp4)
> + %31 = LDRDui %stack.5.tmp8, 0 :: (dereferenceable load 8 from %ir.tmp8)
> + %32 = FCVTZSUWDr killed %31
> + %34 = IMPLICIT_DEF
> + %33 = INSERT_SUBREG %34, %32, 15
> + %35 = SBFMXri killed %33, 61, 31
> + %36 = LDRDroX killed %30, %35, 0, 0 :: (load 8 from %ir.tmp74)
> + %37 = LDRXui %stack.2.tmp5, 0 :: (dereferenceable load 8 from %ir.tmp5)
> + %38 = ADDWri %32, 20, 0
> + %39 = SMADDLrrr killed %38, %24, killed %37
> + STRDroX killed %36, killed %39, %35, 0, 0 :: (store 8 into %ir.tmp85)
> + %40 = LOADgot target-flags(aarch64-got) @IntGlob
> + %41 = MOVi64imm 4617315517961601024
> + STRXui killed %41, killed %40, 0 :: (store 8 into @IntGlob)
> + %42 = LDRWui %stack.0.tmp, 0 :: (dereferenceable load 4 from %ir.tmp)
> + %w0 = COPY %42
> + RET_ReallyLR implicit %w0
> +
> +...
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