[llvm] r319220 - [aarch64][globalisel] Add missing tests from r319216
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 12:27:59 PST 2017
Author: dsanders
Date: Tue Nov 28 12:27:59 2017
New Revision: 319220
URL: http://llvm.org/viewvc/llvm-project?rev=319220&view=rev
Log:
[aarch64][globalisel] Add missing tests from r319216
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir?rev=319220&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir Tue Nov 28 12:27:59 2017
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @cmpxchg_i8(i8* %addr) { ret void }
+ define void @cmpxchg_i16(i16* %addr) { ret void }
+ define void @cmpxchg_i32(i32* %addr) { ret void }
+ define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name: cmpxchg_i8
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[CST2:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
+ ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1 on %ir.addr)
+ ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
+ ; CHECK: %w0 = COPY [[RES2]]
+ %0:_(p0) = COPY %x0
+ %1:_(s8) = G_CONSTANT i8 1
+ %2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 1 on %ir.addr)
+ %3:_(s32) = G_ANYEXT %2
+ %w0 = COPY %3(s32)
+...
+
+---
+name: cmpxchg_i16
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
+ ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 2 on %ir.addr)
+ ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
+ ; CHECK: %w0 = COPY [[RES2]]
+ %0:_(p0) = COPY %x0
+ %1:_(s16) = G_CONSTANT i16 1
+ %2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 2 on %ir.addr)
+ %3:_(s32) = G_ANYEXT %2
+ %w0 = COPY %3(s32)
+...
+
+---
+name: cmpxchg_i32
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4 on %ir.addr)
+ ; CHECK: %w0 = COPY [[RES]]
+ %0:_(p0) = COPY %x0
+ %1:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 4 on %ir.addr)
+ %w0 = COPY %2(s32)
+...
+
+---
+name: cmpxchg_i64
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8 on %ir.addr)
+ ; CHECK: %x0 = COPY [[RES]]
+ %0:_(p0) = COPY %x0
+ %1:_(s64) = G_CONSTANT i64 1
+ %2:_(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
+ %x0 = COPY %2(s64)
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir?rev=319220&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir Tue Nov 28 12:27:59 2017
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @cmpxchg_i8(i8* %addr) { ret void }
+ define void @cmpxchg_i16(i16* %addr) { ret void }
+ define void @cmpxchg_i32(i32* %addr) { ret void }
+ define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name: cmpxchg_i8
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[CMPT:%[0-9]+]]:_(s8) = G_TRUNC [[CMP]]
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[CSTT:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
+ ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 1 on %ir.addr)
+ ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s8)
+ ; CHECK: %w0 = COPY [[RES2]]
+ %0:_(p0) = COPY %x0
+ %1:_(s8) = G_CONSTANT i8 0
+ %2:_(s8) = G_CONSTANT i8 1
+ %3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 1 on %ir.addr)
+ %4:_(s32) = G_ANYEXT %3
+ %w0 = COPY %4(s32)
+...
+
+---
+name: cmpxchg_i16
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[CMPT:%[0-9]+]]:_(s16) = G_TRUNC [[CMP]]
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[CSTT:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
+ ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 2 on %ir.addr)
+ ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s16)
+ ; CHECK: %w0 = COPY [[RES2]]
+ %0:_(p0) = COPY %x0
+ %1:_(s16) = G_CONSTANT i16 0
+ %2:_(s16) = G_CONSTANT i16 1
+ %3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 2 on %ir.addr)
+ %4:_(s32) = G_ANYEXT %3
+ %w0 = COPY %4(s32)
+...
+
+---
+name: cmpxchg_i32
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 4 on %ir.addr)
+ ; CHECK: %w0 = COPY [[RES]]
+ %0:_(p0) = COPY %x0
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_CONSTANT i32 1
+ %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr)
+ %w0 = COPY %3(s32)
+...
+
+---
+name: cmpxchg_i64
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK-LABEL: name: cmpxchg_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
+ ; CHECK: %x0 = COPY [[RES]]
+ %0:_(p0) = COPY %x0
+ %1:_(s64) = G_CONSTANT i64 0
+ %2:_(s64) = G_CONSTANT i64 1
+ %3:_(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+ %x0 = COPY %3(s64)
+...
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