[llvm] r319204 - [Hexagon] Make sure to zero-extend bytes before building a vector

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Nov 28 11:13:17 2017
New Revision: 319204

URL: http://llvm.org/viewvc/llvm-project?rev=319204&view=rev
Log:
[Hexagon] Make sure to zero-extend bytes before building a vector

Added:
    llvm/trunk/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=319204&r1=319203&r2=319204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Nov 28 11:13:17 2017
@@ -2499,16 +2499,18 @@ HexagonTargetLowering::buildVector32(Arr
   //   (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
   //   (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
   SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
-  SDValue S16 = DAG.getConstant(16, dl, MVT::i32);
-  SDValue V0 = DAG.getZExtOrTrunc(Elem[0], dl, MVT::i32);
-  SDValue V1 = DAG.getZExtOrTrunc(Elem[2], dl, MVT::i32);
-  SDValue V2 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[1], S8});
-  SDValue V3 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[3], S8});
-  SDValue V4 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V2});
-  SDValue V5 = DAG.getNode(ISD::OR, dl, MVT::i32, {V1, V3});
-  SDValue V6 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V5, S16});
-  SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V4, V6});
-  return DAG.getBitcast(MVT::v4i8, V7);
+  SDValue V0 = DAG.getZeroExtendInReg(Elem[0], dl, MVT::i8);
+  SDValue V1 = DAG.getZeroExtendInReg(Elem[1], dl, MVT::i8);
+  SDValue V2 = DAG.getZeroExtendInReg(Elem[2], dl, MVT::i8);
+  SDValue V3 = DAG.getZeroExtendInReg(Elem[3], dl, MVT::i8);
+
+  SDValue V4 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V1, S8});
+  SDValue V5 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V3, S8});
+  SDValue V6 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V4});
+  SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V2, V5});
+  SDNode *T0 = DAG.getMachineNode(Hexagon::A2_combine_ll, dl, MVT::i32,
+                                  {V7, V6});
+  return DAG.getBitcast(MVT::v4i8, SDValue(T0,0));
 }
 
 SDValue

Added: llvm/trunk/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll?rev=319204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll Tue Nov 28 11:13:17 2017
@@ -0,0 +1,17 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that we generate zero-extends, instead of just shifting and oring
+; registers (which can contain sign-extended negative values).
+; CHECK: and(r{{[0-9]+}},#255)
+
+define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 {
+b4:
+  %v5 = insertelement <4 x i8> undef, i8 %a0, i32 0
+  %v6 = insertelement <4 x i8> %v5, i8 %a1, i32 1
+  %v7 = insertelement <4 x i8> %v6, i8 %a2, i32 2
+  %v8 = insertelement <4 x i8> %v7, i8 %a3, i32 3
+  %v9 = bitcast <4 x i8> %v8 to i32
+  ret i32 %v9
+}
+
+attributes #0 = { nounwind readnone }