[llvm] r319185 - DAG: Legalize truncstores to illegal int types

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 28 09:11:30 PST 2017


Author: arsenm
Date: Tue Nov 28 09:11:30 2017
New Revision: 319185

URL: http://llvm.org/viewvc/llvm-project?rev=319185&view=rev
Log:
DAG: Legalize truncstores to illegal int types

Truncate to a legal int type, and produce a new
truncstore from a narrower type.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=319185&r1=319184&r2=319185&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Nov 28 09:11:30 2017
@@ -624,13 +624,23 @@ void SelectionDAGLegalize::LegalizeStore
       assert(!StVT.isVector() &&
              "Vector Stores are handled in LegalizeVectorOps");
 
+      SDValue Result;
+
       // TRUNCSTORE:i16 i32 -> STORE i16
-      assert(TLI.isTypeLegal(StVT) &&
-             "Do not know how to expand this store!");
-      Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
-      SDValue Result =
-          DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
-                       Alignment, MMOFlags, AAInfo);
+      if (TLI.isTypeLegal(StVT)) {
+        Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
+        Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
+                              Alignment, MMOFlags, AAInfo);
+      } else {
+        // The in-memory type isn't legal. Truncate to the type it would promote
+        // to, and then do a truncstore.
+        Value = DAG.getNode(ISD::TRUNCATE, dl,
+                            TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
+                            Value);
+        Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
+                                   StVT, Alignment, MMOFlags, AAInfo);
+      }
+
       ReplaceNode(SDValue(Node, 0), Result);
       break;
     }

Added: llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll?rev=319185&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll Tue Nov 28 09:11:30 2017
@@ -0,0 +1,56 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
+
+; GCN-LABEL: {{^}}local_store_i56:
+; GCN-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6
+; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
+; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}}
+define void @local_store_i56(i56 addrspace(3)* %ptr, i56 %arg) #0 {
+  store i56 %arg, i56 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}local_store_i55:
+; GCN-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6
+; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
+; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}}
+define amdgpu_kernel void @local_store_i55(i55 addrspace(3)* %ptr, i55 %arg) #0 {
+  store i55 %arg, i55 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}local_store_i48:
+; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
+; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}}
+define amdgpu_kernel void @local_store_i48(i48 addrspace(3)* %ptr, i48 %arg) #0 {
+  store i48 %arg, i48 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}local_store_i65:
+; GCN-DAG: ds_write_b8 v{{[0-9]+}}, v0 offset:8
+; GCN-DAG: ds_write_b64
+define amdgpu_kernel void @local_store_i65(i65 addrspace(3)* %ptr, i65 %arg) #0 {
+  store i65 %arg, i65 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}local_store_i13:
+; GCN: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x1fff, v1
+; GCN: ds_write_b16 v0, [[TRUNC]]
+define void @local_store_i13(i13 addrspace(3)* %ptr, i13 %arg) #0 {
+  store i13 %arg, i13 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}local_store_i17:
+; GCN: ds_write_b16 v0
+; CIVI: ds_write_b8 v0, v{{[0-9]+}} offset:2
+; GFX9: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:2
+define void @local_store_i17(i17 addrspace(3)* %ptr, i17 %arg) #0 {
+  store i17 %arg, i17 addrspace(3)* %ptr, align 8
+  ret void
+}
+
+attributes #0 = { nounwind }




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