[llvm] r319141 - MachineVerifier: Improve register operand checks
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 19:54:20 PST 2017
Author: matze
Date: Mon Nov 27 19:54:20 2017
New Revision: 319141
URL: http://llvm.org/viewvc/llvm-project?rev=319141&view=rev
Log:
MachineVerifier: Improve register operand checks
This fixes cases where we wouldn't perform various register operand
checks just because we didn't happen to have a definition in the
MCInstrDesc. This changes the code to only skip the tests that actually
depend on the MCInstrDesc definition.
This makes the machine verifier spot the problem from
https://llvm.org/PR33071 after the pass that actually caused it.
Modified:
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=319141&r1=319140&r2=319141&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Nov 27 19:54:20 2017
@@ -1085,14 +1085,14 @@ MachineVerifier::visitMachineOperand(con
report("Two-address instruction operands must be identical", MO, MONum);
// Check register classes.
- if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
- unsigned SubIdx = MO->getSubReg();
+ unsigned SubIdx = MO->getSubReg();
- if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
- if (SubIdx) {
- report("Illegal subregister index for physical register", MO, MONum);
- return;
- }
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ if (SubIdx) {
+ report("Illegal subregister index for physical register", MO, MONum);
+ return;
+ }
+ if (MONum < MCID.getNumOperands()) {
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) {
@@ -1101,85 +1101,88 @@ MachineVerifier::visitMachineOperand(con
<< TRI->getRegClassName(DRC) << " register.\n";
}
}
- } else {
- // Virtual register.
- const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
- if (!RC) {
- // This is a generic virtual register.
-
- // If we're post-Select, we can't have gvregs anymore.
- if (isFunctionSelected) {
- report("Generic virtual register invalid in a Selected function",
- MO, MONum);
- return;
- }
+ }
+ } else {
+ // Virtual register.
+ const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
+ if (!RC) {
+ // This is a generic virtual register.
+
+ // If we're post-Select, we can't have gvregs anymore.
+ if (isFunctionSelected) {
+ report("Generic virtual register invalid in a Selected function",
+ MO, MONum);
+ return;
+ }
- // The gvreg must have a type and it must not have a SubIdx.
- LLT Ty = MRI->getType(Reg);
- if (!Ty.isValid()) {
- report("Generic virtual register must have a valid type", MO,
- MONum);
- return;
- }
+ // The gvreg must have a type and it must not have a SubIdx.
+ LLT Ty = MRI->getType(Reg);
+ if (!Ty.isValid()) {
+ report("Generic virtual register must have a valid type", MO,
+ MONum);
+ return;
+ }
- const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
+ const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
- // If we're post-RegBankSelect, the gvreg must have a bank.
- if (!RegBank && isFunctionRegBankSelected) {
- report("Generic virtual register must have a bank in a "
- "RegBankSelected function",
- MO, MONum);
- return;
- }
+ // If we're post-RegBankSelect, the gvreg must have a bank.
+ if (!RegBank && isFunctionRegBankSelected) {
+ report("Generic virtual register must have a bank in a "
+ "RegBankSelected function",
+ MO, MONum);
+ return;
+ }
- // Make sure the register fits into its register bank if any.
- if (RegBank && Ty.isValid() &&
- RegBank->getSize() < Ty.getSizeInBits()) {
- report("Register bank is too small for virtual register", MO,
- MONum);
- errs() << "Register bank " << RegBank->getName() << " too small("
- << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
- << "-bits\n";
- return;
- }
- if (SubIdx) {
- report("Generic virtual register does not subregister index", MO,
- MONum);
- return;
- }
+ // Make sure the register fits into its register bank if any.
+ if (RegBank && Ty.isValid() &&
+ RegBank->getSize() < Ty.getSizeInBits()) {
+ report("Register bank is too small for virtual register", MO,
+ MONum);
+ errs() << "Register bank " << RegBank->getName() << " too small("
+ << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
+ << "-bits\n";
+ return;
+ }
+ if (SubIdx) {
+ report("Generic virtual register does not subregister index", MO,
+ MONum);
+ return;
+ }
- // If this is a target specific instruction and this operand
- // has register class constraint, the virtual register must
- // comply to it.
- if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
- TII->getRegClass(MCID, MONum, TRI, *MF)) {
- report("Virtual register does not match instruction constraint", MO,
- MONum);
- errs() << "Expect register class "
- << TRI->getRegClassName(
- TII->getRegClass(MCID, MONum, TRI, *MF))
- << " but got nothing\n";
- return;
- }
+ // If this is a target specific instruction and this operand
+ // has register class constraint, the virtual register must
+ // comply to it.
+ if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
+ MONum < MCID.getNumOperands() &&
+ TII->getRegClass(MCID, MONum, TRI, *MF)) {
+ report("Virtual register does not match instruction constraint", MO,
+ MONum);
+ errs() << "Expect register class "
+ << TRI->getRegClassName(
+ TII->getRegClass(MCID, MONum, TRI, *MF))
+ << " but got nothing\n";
+ return;
+ }
- break;
+ break;
+ }
+ if (SubIdx) {
+ const TargetRegisterClass *SRC =
+ TRI->getSubClassWithSubReg(RC, SubIdx);
+ if (!SRC) {
+ report("Invalid subregister index for virtual register", MO, MONum);
+ errs() << "Register class " << TRI->getRegClassName(RC)
+ << " does not support subreg index " << SubIdx << "\n";
+ return;
}
- if (SubIdx) {
- const TargetRegisterClass *SRC =
- TRI->getSubClassWithSubReg(RC, SubIdx);
- if (!SRC) {
- report("Invalid subregister index for virtual register", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not support subreg index " << SubIdx << "\n";
- return;
- }
- if (RC != SRC) {
- report("Invalid register class for subregister index", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not fully support subreg index " << SubIdx << "\n";
- return;
- }
+ if (RC != SRC) {
+ report("Invalid register class for subregister index", MO, MONum);
+ errs() << "Register class " << TRI->getRegClassName(RC)
+ << " does not fully support subreg index " << SubIdx << "\n";
+ return;
}
+ }
+ if (MONum < MCID.getNumOperands()) {
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (SubIdx) {
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