[PATCH] D40003: [RISCV] MC layer support for the rest instructions of standard compress instruction set

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 124326.
shiva0217 edited the summary of this revision.
shiva0217 added a comment.

1. Add test case to check the instruction operands should not x0.

2. Add GPRNonX0X2 register class and test case for c.lui.


Repository:
  rL LLVM

https://reviews.llvm.org/D40003

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  lib/Target/RISCV/RISCVInstrFormatsC.td
  lib/Target/RISCV/RISCVInstrInfoC.td
  lib/Target/RISCV/RISCVRegisterInfo.td
  test/MC/RISCV/rv32c-invalid.s
  test/MC/RISCV/rv32c-valid.s
  test/MC/RISCV/rv64c-invalid.s
  test/MC/RISCV/rv64c-valid.s

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