[PATCH] D31852: [PowerPC] Convert reg/reg instructions fed by constants to reg/imm instructions (pre and post RA)

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai updated this revision to Diff 124209.
nemanjai added a comment.

Fix handling for R0/X0 where it's special.
Add test cases for the special handling there.
Turn the peepholes on by default.
Fix test cases that change due to having this on by default.


Repository:
  rL LLVM

https://reviews.llvm.org/D31852

Files:
  lib/Target/PowerPC/CMakeLists.txt
  lib/Target/PowerPC/PPC.h
  lib/Target/PowerPC/PPCInstrInfo.cpp
  lib/Target/PowerPC/PPCInstrInfo.h
  lib/Target/PowerPC/PPCMIPeephole.cpp
  lib/Target/PowerPC/PPCPreEmitPeephole.cpp
  lib/Target/PowerPC/PPCTargetMachine.cpp
  test/CodeGen/PowerPC/build-vector-tests.ll
  test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
  test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
  test/CodeGen/PowerPC/fast-isel-call.ll
  test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
  test/CodeGen/PowerPC/unaligned.ll
  test/CodeGen/PowerPC/variable_elem_vec_extracts.ll

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