[llvm] r318915 - [ARM GlobalISel] Support G_FDIV for s32 and s64
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 23 05:26:07 PST 2017
Author: rovka
Date: Thu Nov 23 05:26:07 2017
New Revision: 318915
URL: http://llvm.org/viewvc/llvm-project?rev=318915&view=rev
Log:
[ARM GlobalISel] Support G_FDIV for s32 and s64
TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.
For the legalizer and reg bank select, we do the same thing as for the
other floating point binary operations: either mark as legal if we have
a FP unit or lower to a libcall, and map to the floating point
registers.
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Nov 23 05:26:07 2017
@@ -97,6 +97,9 @@ static RTLIB::Libcall getRTLibDesc(unsig
case TargetOpcode::G_FMUL:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
+ case TargetOpcode::G_FDIV:
+ assert((Size == 32 || Size == 64) && "Unsupported size");
+ return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
case TargetOpcode::G_FREM:
return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
case TargetOpcode::G_FPOW:
@@ -154,6 +157,7 @@ LegalizerHelper::libcall(MachineInstr &M
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV:
case TargetOpcode::G_FPOW:
case TargetOpcode::G_FREM: {
Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu Nov 23 05:26:07 2017
@@ -148,7 +148,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({G_ICMP, 1, Ty}, Legal);
if (!ST.useSoftFloat() && ST.hasVFP2()) {
- for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL})
+ for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
for (auto Ty : {s32, s64})
setAction({BinOp, Ty}, Legal);
@@ -159,7 +159,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({G_FCMP, 1, s32}, Legal);
setAction({G_FCMP, 1, s64}, Legal);
} else {
- for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL})
+ for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
for (auto Ty : {s32, s64})
setAction({BinOp, Ty}, Libcall);
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Nov 23 05:26:07 2017
@@ -244,7 +244,8 @@ ARMRegisterBankInfo::getInstrMapping(con
}
case G_FADD:
case G_FSUB:
- case G_FMUL: {
+ case G_FMUL:
+ case G_FDIV: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OperandsMapping =Ty.getSizeInBits() == 64
? &ARM::ValueMappings[ARM::DPR3OpsIdx]
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu Nov 23 05:26:07 2017
@@ -20,6 +20,9 @@
define void @test_fmul_s32() #0 { ret void }
define void @test_fmul_s64() #0 { ret void }
+ define void @test_fdiv_s32() #0 { ret void }
+ define void @test_fdiv_s64() #0 { ret void }
+
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
@@ -501,6 +504,66 @@ body: |
%d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %d0
+ ; CHECK: BX_RET 14, _, implicit %d0
+...
+---
+name: test_fdiv_s32
+# CHECK-LABEL: name: test_fdiv_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+
+ %1(s32) = COPY %s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+ %2(s32) = G_FDIV %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, _
+
+ %s0 = COPY %2(s32)
+ ; CHECK: %s0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %s0
+ ; CHECK: BX_RET 14, _, implicit %s0
+...
+---
+name: test_fdiv_s64
+# CHECK-LABEL: name: test_fdiv_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+
+ %1(s64) = COPY %d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+
+ %2(s64) = G_FDIV %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, _
+
+ %d0 = COPY %2(s64)
+ ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Thu Nov 23 05:26:07 2017
@@ -17,6 +17,9 @@
define void @test_fmul_float() { ret void }
define void @test_fmul_double() { ret void }
+ define void @test_fdiv_float() { ret void }
+ define void @test_fdiv_double() { ret void }
+
define void @test_fcmp_true_s32() { ret void }
define void @test_fcmp_false_s32() { ret void }
@@ -503,6 +506,93 @@ body: |
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32)
+ %r1 = COPY %8(s32)
+ BX_RET 14, _, implicit %r0, implicit %r1
+...
+---
+name: test_fdiv_float
+# CHECK-LABEL: name: test_fdiv_float
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; HARD: [[R:%[0-9]+]]:_(s32) = G_FDIV [[X]], [[Y]]
+ ; SOFT-NOT: G_FDIV
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-DAG: %r0 = COPY [[X]]
+ ; SOFT-DAG: %r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL $__aeabi_fdiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+ ; SOFT-DEFAULT: BL $__divsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FDIV
+ %2(s32) = G_FDIV %0, %1
+ ; CHECK: %r0 = COPY [[R]]
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_fdiv_double
+# CHECK-LABEL: name: test_fdiv_double
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1, %r2, %r3
+
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = COPY %r2
+ %3(s32) = COPY %r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+ ; HARD: [[R:%[0-9]+]]:_(s64) = G_FDIV [[X]], [[Y]]
+ ; SOFT-NOT: G_FDIV
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL $__aeabi_ddiv, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DEFAULT: BL $__divdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FDIV
+ %6(s64) = G_FDIV %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+ %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
+ %r0 = COPY %7(s32)
%r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=318915&r1=318914&r2=318915&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu Nov 23 05:26:07 2017
@@ -49,6 +49,9 @@
define void @test_fmul_s32() #0 { ret void }
define void @test_fmul_s64() #0 { ret void }
+ define void @test_fdiv_s32() #0 { ret void }
+ define void @test_fdiv_s64() #0 { ret void }
+
define void @test_soft_fp_s64() #0 { ret void }
attributes #0 = { "target-features"="+vfp2"}
@@ -885,6 +888,58 @@ body: |
%d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0
+...
+---
+name: test_fdiv_s32
+# CHECK-LABEL: name: test_fdiv_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FDIV %0, %1
+ %s0 = COPY %2(s32)
+ BX_RET 14, _, implicit %s0
+
+...
+---
+name: test_fdiv_s64
+# CHECK-LABEL: name: test_fdiv_s64
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FDIV %0, %1
+ %d0 = COPY %2(s64)
+ BX_RET 14, _, implicit %d0
+
...
---
name: test_soft_fp_s64
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