[PATCH] D40383: Add RISCV privileged instructions

[David Craven via Phabricator via llvm-commits]

dvc94ch updated this revision to Diff 124060.
dvc94ch added a comment.

Addressed all comments.

rename priv.s to priv-valid.s, added priv-invalid.s, removed ecall/ebreak test cases (where added because those instructions are explicitly mentioned in priv spec)

renamed tablegen class to Priv, added isTerminator, isBarrier, isReturn to mret, sret, uret


https://reviews.llvm.org/D40383

Files:
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/priv-invalid.s
  test/MC/RISCV/priv-valid.s


Index: test/MC/RISCV/priv-valid.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/priv-valid.s
@@ -0,0 +1,32 @@
+# RUN: llvm-mc %s -triple=riscv32 -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: uret
+# CHECK: encoding: [0x73,0x00,0x20,0x00]
+uret
+
+# CHECK-INST: sret
+# CHECK: encoding: [0x73,0x00,0x20,0x10]
+sret
+
+# CHECK-INST: mret
+# CHECK: encoding: [0x73,0x00,0x20,0x30]
+mret
+
+# CHECK-INST: wfi
+# CHECK: encoding: [0x73,0x00,0x50,0x10]
+wfi
+
+# CHECK-INST: sfence.vma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x12]
+sfence.vma zero, zero
+
+# CHECK-INST: sfence.vma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x12]
+sfence.vma a0, a1
Index: test/MC/RISCV/priv-invalid.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/priv-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+
+mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+
+sfence.vma zero # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+
+sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -574,3 +574,44 @@
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
+
+//===----------------------------------------------------------------------===//
+// Privileged instructions
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class Priv<string opcodestr>
+    : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, "">;
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+  def URET : Priv<"uret"> {
+    let rs1 = 0;
+    let rd = 0;
+    let imm12 = 0b000000000010;
+  }
+
+  def SRET : Priv<"sret"> {
+    let rs1 = 0;
+    let rd = 0;
+    let imm12 = 0b000100000010;
+  }
+
+  def MRET : Priv<"mret"> {
+    let rs1 = 0;
+    let rd = 0;
+    let imm12 = 0b001100000010;
+  }
+}
+
+def WFI : Priv<"wfi"> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b000100000101;
+}
+
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+def SFENCEVMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
+                        (ins GPR:$rs1, GPR:$rs2),
+                        "sfence.vma", "$rs1, $rs2"> {
+  let rd = 0;
+}


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