[PATCH] D40003: [RISCV] MC layer support for the rest instructions of standard compress instruction set

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 124040.
shiva0217 edited the summary of this revision.
shiva0217 added a comment.

1. Update test cases that test the immediate value max/min in -valids.s and just outside the range in -invalid.s.

2. List the instruction patterns base on the table in section 12.7 "RVC Instruction Set Listings" (page 82 and 83).

3. Update immediate operand constraints UImm5NonZero/UImm6NonZero/UImm10Lsb00NonZero to reflect that the instructions do not allow zero immediate value.


Repository:
  rL LLVM

https://reviews.llvm.org/D40003

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  lib/Target/RISCV/RISCVInstrFormatsC.td
  lib/Target/RISCV/RISCVInstrInfoC.td
  test/MC/RISCV/rv32c-invalid.s
  test/MC/RISCV/rv32c-valid.s
  test/MC/RISCV/rv64c-invalid.s
  test/MC/RISCV/rv64c-valid.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D40003.124040.patch
Type: text/x-patch
Size: 20409 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171123/5fb292a8/attachment.bin>