[PATCH] D40348: [PowerPC] Follow-up to r318436 to get the missed CSE opportunities

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.

In r318436, the PPC back end improved the code-gen for stores of constant values. However, there's a class of patterns that this misses and a class that it actually makes worse.

- The revision isn't able to do anything for indexed stores (pre-inc in the case of PPC) as the target-specific DAG combine isn't run on the indexed stores produced by the generic combiner.
- The revision makes code-gen worse for 8-32 bit stores of negative values as the new 64-bit constant isn't sign-extended so just appears to be a large positive value. Example:

  extern int IVal;
  void test() {
    IVal = -7;
  }

Generates this code:

  li 4, 0
  oris 4, 4, 65535
  ori 4, 4, 65529
  stw 4, 0(3)

Rather than the obviously better:

  li 4, -7
  stw 4, 0(3)

This patch does the following:

- Modifies the generic DAG combiner to add the new indexed LD/ST to the worklist so the target-specific combiner has an opportunity to fix it up
- Sign-extends the constant to 64-bit from the bit width of `MemoryVT`
- Canonicalizes the materialization of constants that fit in a 16-bit signed field so that the DAG can CSE them as expected (i.e. 64-bit constants are always materialized as values sign-extended to 64 bits)

The result is

- Pre-inc loads are handled
- Good code-gen for storing negative constants
- CSE for all 64-bit constants that can be emitted using just the PPC "Load-immediate" instruction


Repository:
  rL LLVM

https://reviews.llvm.org/D40348

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/CodeGen/PowerPC/store-constant.ll

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