[PATCH] D39195: [ARM] Add diagnostics for SPR/DPR lists

[Oliver Stannard via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL318766: [ARM] Add diagnostics for SPR/DPR lists (authored by olista01).

Changed prior to commit:
  https://reviews.llvm.org/D39195?vs=119887&id=123786#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D39195

Files:
  llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
  llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/trunk/test/MC/ARM/vldm-vstm-diags.s


Index: llvm/trunk/test/MC/ARM/vldm-vstm-diags.s
===================================================================
--- llvm/trunk/test/MC/ARM/vldm-vstm-diags.s
+++ llvm/trunk/test/MC/ARM/vldm-vstm-diags.s
@@ -0,0 +1,44 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null             %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D32
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null -mattr=+d16 %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D16
+
+  // First operand must be a GPR
+  vldm s0, {s1, s2}
+// CHECK: error: operand must be a register in range [r0, r15]
+// CHECK-NEXT: vldm s0, {s1, s2}
+
+  vstm s0, {s1, s2}
+// CHECK: error: operand must be a register in range [r0, r15]
+// CHECK-NEXT: vstm s0, {s1, s2}
+
+
+  // Second operand must be a list of SPRs or DPRs
+  vldm r0, {r1, r2}
+// CHECK: error: invalid instruction, any one of the following would fix this:
+// CHECK-NEXT: vldm r0, {r1, r2}
+// CHECK: note: operand must be a list of registers in range [s0, s31]
+// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
+// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
+  vldm r0, #42
+// CHECK: error: invalid instruction, any one of the following would fix this:
+// CHECK-NEXT: vldm r0, #42
+// CHECK: note: operand must be a list of registers in range [s0, s31]
+// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
+// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
+  vldm r0, {s1, d2}
+// CHECK: error: invalid register in register list
+// CHECK-NEXT: vldm r0, {s1, d2}
+  vstm r0, {r1, r2}
+// CHECK: error: invalid instruction, any one of the following would fix this:
+// CHECK-NEXT: vstm r0, {r1, r2}
+// CHECK: note: operand must be a list of registers in range [s0, s31]
+// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
+// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
+  vstm r0, #42
+// CHECK: error: invalid instruction, any one of the following would fix this:
+// CHECK-NEXT: vstm r0, #42
+// CHECK: note: operand must be a list of registers in range [s0, s31]
+// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
+// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
+  vstm r0, {s1, d2}
+// CHECK: error: invalid register in register list
+// CHECK-NEXT: vstm r0, {s1, d2}
Index: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
@@ -526,15 +526,21 @@
 
 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
 
-def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
+def DPRRegListAsmOperand : AsmOperandClass {
+  let Name = "DPRRegList";
+  let DiagnosticType = "DPR_RegList";
+}
 def dpr_reglist : Operand<i32> {
   let EncoderMethod = "getRegisterListOpValue";
   let ParserMatchClass = DPRRegListAsmOperand;
   let PrintMethod = "printRegisterList";
   let DecoderMethod = "DecodeDPRRegListOperand";
 }
 
-def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
+def SPRRegListAsmOperand : AsmOperandClass {
+  let Name = "SPRRegList";
+  let DiagnosticString = "operand must be a list of registers in range [s0, s31]";
+}
 def spr_reglist : Operand<i32> {
   let EncoderMethod = "getRegisterListOpValue";
   let ParserMatchClass = SPRRegListAsmOperand;
Index: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -10137,6 +10137,9 @@
   case Match_DPR:
     return hasD16() ? "operand must be a register in range [d0, d15]"
                     : "operand must be a register in range [d0, d31]";
+  case Match_DPR_RegList:
+    return hasD16() ? "operand must be a list of registers in range [d0, d15]"
+                    : "operand must be a list of registers in range [d0, d31]";
 
   // For all other diags, use the static string from tablegen.
   default:


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