[llvm] r318749 - [MI scheduler] Fix VADD and VSUB in cortex-a57 model

[Eugene Leviant via llvm-commits]

Author: evgeny777
Date: Tue Nov 21 03:01:28 2017
New Revision: 318749

URL: http://llvm.org/viewvc/llvm-project?rev=318749&view=rev
Log:
[MI scheduler] Fix VADD and VSUB in cortex-a57 model

This patch fixes instregex for interger vector add/sub instructions

Differential revision: https://reviews.llvm.org/D40254

Added:
    llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll
    llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMScheduleA57.td

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA57.td?rev=318749&r1=318748&r2=318749&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA57.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA57.td Tue Nov 21 03:01:28 2017
@@ -971,9 +971,9 @@ def : InstRW<[A57WriteVABAL, A57ReadVABA
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>;
 
 // ASIMD arith, basic
-def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW",
+def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW",
   "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",
-  "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>;
+  "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>;
 
 // ASIMD arith, complex
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB",

Added: llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll?rev=318749&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll Tue Nov 21 03:01:28 2017
@@ -0,0 +1,26 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  addv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VADDv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) {
+  %3 = add <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  addv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VADDfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @addv_f32(<4 x float>, <4 x float>) {
+  %3 = fadd <4 x float> %0, %1
+  ret <4 x float> %3
+}

Added: llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll?rev=318749&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll Tue Nov 21 03:01:28 2017
@@ -0,0 +1,26 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  subv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) {
+  %3 = sub <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  subv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @subv_f32(<4 x float>, <4 x float>) {
+  %3 = fsub <4 x float> %0, %1
+  ret <4 x float> %3
+}