[PATCH] D40254: [MI scheduler] Fix VADD in cortex-a57 model

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.

The "VADD" regex incorrectly captures VADDfq and other vector floating-point adds, which have 5 cycles latency instead of 3.


Repository:
  rL LLVM

https://reviews.llvm.org/D40254

Files:
  lib/Target/ARM/ARMScheduleA57.td
  test/CodeGen/ARM/cortex-a57-misched-vadd.ll


Index: test/CodeGen/ARM/cortex-a57-misched-vadd.ll
===================================================================
--- test/CodeGen/ARM/cortex-a57-misched-vadd.ll
+++ test/CodeGen/ARM/cortex-a57-misched-vadd.ll
@@ -0,0 +1,24 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK:        SU(8): {{.*}} VADDv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+; CHECK:        SU(8): {{.*}} VADDfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) {
+  %3 = add <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+define <4 x float> @addv_f32(<4 x float>, <4 x float>) {
+  %3 = fadd <4 x float> %0, %1
+  ret <4 x float> %3
+}
Index: lib/Target/ARM/ARMScheduleA57.td
===================================================================
--- lib/Target/ARM/ARMScheduleA57.td
+++ lib/Target/ARM/ARMScheduleA57.td
@@ -971,7 +971,7 @@
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>;
 
 // ASIMD arith, basic
-def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW",
+def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW",
   "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",
   "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>;
 


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