[llvm] r318643 - [ARM GlobalISel] Add test for RSBri. NFC

[Diana Picus via llvm-commits]

Author: rovka
Date: Mon Nov 20 03:05:31 2017
New Revision: 318643

URL: http://llvm.org/viewvc/llvm-project?rev=318643&view=rev
Log:
[ARM GlobalISel] Add test for RSBri. NFC

Add instruction selector test for RSBri, which is derived from
AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is
derived from the very similar AsI1_bin_irs pattern.

Modified:
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=318643&r1=318642&r2=318643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Mon Nov 20 03:05:31 2017
@@ -18,6 +18,8 @@
   define void @test_fsub_s64() #0 { ret void }
 
   define void @test_sub_s32() { ret void }
+  define void @test_sub_imm_s32() { ret void }
+  define void @test_sub_rev_imm_s32() { ret void }
 
   define void @test_mul_s32() #1 { ret void }
   define void @test_mulv5_s32() { ret void }
@@ -466,6 +468,62 @@ body:             |
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name:            test_sub_imm_s32
+# CHECK-LABEL: name: test_sub_imm_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+    %1(s32) = G_CONSTANT i32 17
+    %2(s32) = G_SUB %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _
+
+    %r0 = COPY %2(s32)
+    ; CHECK: %r0 = COPY [[VREGRES]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name:            test_sub_rev_imm_s32
+# CHECK-LABEL: name: test_sub_rev_imm_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+    %1(s32) = G_CONSTANT i32 17
+    %2(s32) = G_SUB %1, %0
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _
+
+    %r0 = COPY %2(s32)
+    ; CHECK: %r0 = COPY [[VREGRES]]
 
     BX_RET 14, _, implicit %r0
     ; CHECK: BX_RET 14, _, implicit %r0