[PATCH] D40148: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type

[Yaxun Liu via Phabricator via llvm-commits]

yaxunl updated this revision to Diff 123352.
yaxunl retitled this revision from "[AMDGPU] Fix SITargetLowering::lowerEXTRACT_VECTOR_ELT for constant type" to "[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type".
yaxunl edited the summary of this revision.
yaxunl added a comment.

Revised by Matt's comments.


https://reviews.llvm.org/D40148

Files:
  lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll


Index: test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
===================================================================
--- test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=gfx901 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s
 
 ; GCN-LABEL: {{^}}s_insertelement_v2i16_0:
 ; GCN: s_load_dword [[VEC:s[0-9]+]]
Index: lib/Target/X86/X86ISelLowering.h
===================================================================
--- lib/Target/X86/X86ISelLowering.h
+++ lib/Target/X86/X86ISelLowering.h
@@ -662,8 +662,11 @@
     void markLibCallAttributes(MachineFunction *MF, unsigned CC,
                                ArgListTy &Args) const override;
 
-    MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
-      return MVT::i8;
+    // For i512, DAGTypeLegalizer::SplitInteger needs a shift amount 256,
+    // which cannot be held by i8, therefore use i16 instead. In all the
+    // other situations i8 is sufficient.
+    MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
+      return VT.getSizeInBits() >= 512 ? MVT::i16 : MVT::i8;
     }
 
     const MCExpr *
Index: lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -1166,9 +1166,11 @@
   assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
          Op.getValueSizeInBits() && "Invalid integer splitting!");
   Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op);
-  Hi = DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op,
-                   DAG.getConstant(LoVT.getSizeInBits(), dl,
-                                   TLI.getPointerTy(DAG.getDataLayout())));
+  Hi =
+      DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op,
+                  DAG.getConstant(LoVT.getSizeInBits(), dl,
+                                  TLI.getScalarShiftAmountTy(
+                                      DAG.getDataLayout(), Op.getValueType())));
   Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
 }
 


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