[llvm] r318490 - Fix a bunch more layering of CodeGen headers that are in Target
David Blaikie via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 16 17:07:12 PST 2017
Author: dblaikie
Date: Thu Nov 16 17:07:10 2017
New Revision: 318490
URL: http://llvm.org/viewvc/llvm-project?rev=318490&view=rev
Log:
Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).
Added:
llvm/trunk/include/llvm/CodeGen/CostTable.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/CostTable.h
llvm/trunk/include/llvm/CodeGen/TargetCallingConv.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetCallingConv.h
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFile.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
llvm/trunk/include/llvm/CodeGen/TargetOpcodes.def
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/include/llvm/CodeGen/TargetOpcodes.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetOpcodes.h
llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h
- copied, changed from r318489, llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
Removed:
llvm/trunk/include/llvm/Target/CostTable.h
llvm/trunk/include/llvm/Target/TargetCallingConv.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/include/llvm/Target/TargetOpcodes.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
Modified:
llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h
llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
llvm/trunk/include/llvm/CodeGen/FastISel.h
llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h
llvm/trunk/include/llvm/CodeGen/LiveRangeEdit.h
llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h
llvm/trunk/include/llvm/CodeGen/LiveVariables.h
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h
llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/include/llvm/CodeGen/TailDuplicator.h
llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h
llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
llvm/trunk/include/llvm/CodeGen/VirtRegMap.h
llvm/trunk/include/llvm/module.modulemap
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h
llvm/trunk/lib/CodeGen/Analysis.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AddressPool.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/EHStreamer.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp
llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp
llvm/trunk/lib/CodeGen/BasicTargetTransformInfo.cpp
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/CodeGen/BranchRelaxation.cpp
llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
llvm/trunk/lib/CodeGen/CallingConvLower.cpp
llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp
llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp
llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp
llvm/trunk/lib/CodeGen/ExpandMemCmp.cpp
llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/trunk/lib/CodeGen/FEntryInserter.cpp
llvm/trunk/lib/CodeGen/GCRootLowering.cpp
llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp
llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp
llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
llvm/trunk/lib/CodeGen/GlobalMerge.cpp
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
llvm/trunk/lib/CodeGen/InlineSpiller.cpp
llvm/trunk/lib/CodeGen/InterferenceCache.cpp
llvm/trunk/lib/CodeGen/InterleavedAccessPass.cpp
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
llvm/trunk/lib/CodeGen/LiveInterval.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp
llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp
llvm/trunk/lib/CodeGen/LiveRegUnits.cpp
llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp
llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp
llvm/trunk/lib/CodeGen/LowerEmuTLS.cpp
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
llvm/trunk/lib/CodeGen/MachineCSE.cpp
llvm/trunk/lib/CodeGen/MachineCombiner.cpp
llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
llvm/trunk/lib/CodeGen/MachineOutliner.cpp
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/MachineSink.cpp
llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
llvm/trunk/lib/CodeGen/PHIElimination.cpp
llvm/trunk/lib/CodeGen/PatchableFunction.cpp
llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
llvm/trunk/lib/CodeGen/RegAllocBase.cpp
llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
llvm/trunk/lib/CodeGen/RegAllocFast.cpp
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/RegisterPressure.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp
llvm/trunk/lib/CodeGen/SafeStack.cpp
llvm/trunk/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
llvm/trunk/lib/CodeGen/SplitKit.cpp
llvm/trunk/lib/CodeGen/StackColoring.cpp
llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
llvm/trunk/lib/CodeGen/StackMaps.cpp
llvm/trunk/lib/CodeGen/StackProtector.cpp
llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
llvm/trunk/lib/CodeGen/TailDuplicator.cpp
llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
llvm/trunk/lib/CodeGen/TargetOptionsImpl.cpp
llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
llvm/trunk/lib/CodeGen/TargetSchedule.cpp
llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp
llvm/trunk/lib/LTO/LTOCodeGenerator.cpp
llvm/trunk/lib/LTO/LTOModule.cpp
llvm/trunk/lib/LTO/UpdateCompilerUsed.cpp
llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp
llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/AArch64/AArch64TargetObjectFile.h
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/trunk/lib/Target/ARC/ARCAsmPrinter.cpp
llvm/trunk/lib/Target/ARC/ARCFrameLowering.cpp
llvm/trunk/lib/Target/ARC/ARCISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARC/ARCISelLowering.h
llvm/trunk/lib/Target/ARC/ARCRegisterInfo.h
llvm/trunk/lib/Target/ARC/ARCSubtarget.h
llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h
llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp
llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/trunk/lib/Target/AVR/AVRISelLowering.h
llvm/trunk/lib/Target/AVR/AVRRegisterInfo.h
llvm/trunk/lib/Target/AVR/AVRRelaxMemOperations.cpp
llvm/trunk/lib/Target/AVR/AVRSubtarget.h
llvm/trunk/lib/Target/BPF/BPFISelLowering.h
llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
llvm/trunk/lib/Target/BPF/BPFSubtarget.h
llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
llvm/trunk/lib/Target/Hexagon/Hexagon.h
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h
llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp
llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp
llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp
llvm/trunk/lib/Target/Hexagon/RDFRegisters.h
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.h
llvm/trunk/lib/Target/Lanai/LanaiSubtarget.h
llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h
llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h
llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h
llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h
llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h
llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h
llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetObjectFile.h
llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h
llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
llvm/trunk/lib/Target/Sparc/SparcTargetObjectFile.cpp
llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp
llvm/trunk/lib/Target/TargetMachine.cpp
llvm/trunk/lib/Target/TargetMachineC.cpp
llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h
llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp
llvm/trunk/lib/Target/X86/X86CallLowering.cpp
llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
llvm/trunk/lib/Target/X86/X86DomainReassignment.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.cpp
llvm/trunk/lib/Target/X86/X86OptimizeLEAs.cpp
llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp
llvm/trunk/lib/Target/X86/X86TargetObjectFile.h
llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h
llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp
llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h
llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
llvm/trunk/tools/llc/llc.cpp
llvm/trunk/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
llvm/trunk/unittests/MI/LiveIntervalTest.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h Thu Nov 16 17:07:10 2017
@@ -27,6 +27,8 @@
#include "llvm/Analysis/TargetTransformInfoImpl.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CallSite.h"
@@ -46,8 +48,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original)
+++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetCallingConv.h"
namespace llvm {
Copied: llvm/trunk/include/llvm/CodeGen/CostTable.h (from r318489, llvm/trunk/include/llvm/Target/CostTable.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CostTable.h?p2=llvm/trunk/include/llvm/CodeGen/CostTable.h&p1=llvm/trunk/include/llvm/Target/CostTable.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/CostTable.h (original)
+++ llvm/trunk/include/llvm/CodeGen/CostTable.h Thu Nov 16 17:07:10 2017
@@ -12,8 +12,8 @@
///
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_COSTTABLE_H_
-#define LLVM_TARGET_COSTTABLE_H_
+#ifndef LLVM_CODEGEN_COSTTABLE_H_
+#define LLVM_CODEGEN_COSTTABLE_H_
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
@@ -66,5 +66,4 @@ ConvertCostTableLookup(ArrayRef<TypeConv
} // namespace llvm
-
-#endif /* LLVM_TARGET_COSTTABLE_H_ */
+#endif /* LLVM_CODEGEN_COSTTABLE_H_ */
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Nov 16 17:07:10 2017
@@ -20,6 +20,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
@@ -27,7 +28,6 @@
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/IntrinsicInst.h"
-#include "llvm/Target/TargetLowering.h"
#include <algorithm>
#include <cstdint>
#include <utility>
Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Thu Nov 16 17:07:10 2017
@@ -23,11 +23,11 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/KnownBits.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <utility>
#include <vector>
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h Thu Nov 16 17:07:10 2017
@@ -18,10 +18,10 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetCallingConv.h"
#include <cstdint>
#include <functional>
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Thu Nov 16 17:07:10 2017
@@ -23,12 +23,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h Thu Nov 16 17:07:10 2017
@@ -20,13 +20,13 @@
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include <cstdint>
#include <cassert>
+#include <cstdint>
#include <tuple>
-#include <utility>
#include <unordered_map>
+#include <utility>
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Thu Nov 16 17:07:10 2017
@@ -28,11 +28,11 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <utility>
Modified: llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h Thu Nov 16 17:07:10 2017
@@ -32,8 +32,8 @@
#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <utility>
Modified: llvm/trunk/include/llvm/CodeGen/LiveRangeEdit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveRangeEdit.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveRangeEdit.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveRangeEdit.h Thu Nov 16 17:07:10 2017
@@ -29,7 +29,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include <cassert>
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h Thu Nov 16 17:07:10 2017
@@ -16,9 +16,9 @@
#define LLVM_CODEGEN_LIVEREGUNITS_H
#include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdint>
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Thu Nov 16 17:07:10 2017
@@ -36,7 +36,7 @@
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Nov 16 17:07:10 2017
@@ -22,11 +22,11 @@
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/ArrayRecycler.h"
-#include "llvm/Target/TargetOpcodes.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -27,9 +27,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/LaneBitmask.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterClassInfo.h Thu Nov 16 17:07:10 2017
@@ -20,8 +20,8 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <memory>
Modified: llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterPressure.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterPressure.h Thu Nov 16 17:07:10 2017
@@ -20,8 +20,8 @@
#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h Thu Nov 16 17:07:10 2017
@@ -21,8 +21,8 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
class ResourcePriorityQueue;
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Thu Nov 16 17:07:10 2017
@@ -22,8 +22,8 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/iterator.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLowering.h"
#include <cassert>
#include <cstddef>
#include <iterator>
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h Thu Nov 16 17:07:10 2017
@@ -24,9 +24,9 @@
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/LaneBitmask.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <list>
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <memory>
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/TailDuplicator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TailDuplicator.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TailDuplicator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TailDuplicator.h Thu Nov 16 17:07:10 2017
@@ -22,8 +22,8 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
#include <vector>
Copied: llvm/trunk/include/llvm/CodeGen/TargetCallingConv.h (from r318489, llvm/trunk/include/llvm/Target/TargetCallingConv.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetCallingConv.h?p2=llvm/trunk/include/llvm/CodeGen/TargetCallingConv.h&p1=llvm/trunk/include/llvm/Target/TargetCallingConv.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetCallingConv.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetCallingConv.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===-- llvm/Target/TargetCallingConv.h - Calling Convention ----*- C++ -*-===//
+//===-- llvm/CodeGen/TargetCallingConv.h - Calling Convention ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
-#define LLVM_TARGET_TARGETCALLINGCONV_H
+#ifndef LLVM_CODEGEN_TARGETCALLINGCONV_H
+#define LLVM_CODEGEN_TARGETCALLINGCONV_H
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ValueTypes.h"
@@ -201,4 +201,4 @@ namespace ISD {
} // end namespace ISD
} // end namespace llvm
-#endif // LLVM_TARGET_TARGETCALLINGCONV_H
+#endif // LLVM_CODEGEN_TARGETCALLINGCONV_H
Modified: llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/TargetFrameLowering.h ---------------------------*- C++ -*-===//
+//===-- llvm/CodeGen/TargetFrameLowering.h ----------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
Copied: llvm/trunk/include/llvm/CodeGen/TargetLowering.h (from r318489, llvm/trunk/include/llvm/Target/TargetLowering.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLowering.h?p2=llvm/trunk/include/llvm/CodeGen/TargetLowering.h&p1=llvm/trunk/include/llvm/Target/TargetLowering.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===- llvm/Target/TargetLowering.h - Target Lowering Info ------*- C++ -*-===//
+//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -20,8 +20,8 @@
///
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETLOWERING_H
-#define LLVM_TARGET_TARGETLOWERING_H
+#ifndef LLVM_CODEGEN_TARGETLOWERING_H
+#define LLVM_CODEGEN_TARGETLOWERING_H
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
@@ -35,6 +35,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallSite.h"
@@ -51,7 +52,6 @@
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
@@ -3512,4 +3512,4 @@ void GetReturnInfo(Type *ReturnType, Att
} // end namespace llvm
-#endif // LLVM_TARGET_TARGETLOWERING_H
+#endif // LLVM_CODEGEN_TARGETLOWERING_H
Copied: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFile.h (from r318489, llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFile.h?p2=llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFile.h&p1=llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFile.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===-- llvm/Target/TargetLoweringObjectFile.h - Object Info ----*- C++ -*-===//
+//===-- llvm/CodeGen/TargetLoweringObjectFile.h - Object Info ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -12,8 +12,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
-#define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
+#ifndef LLVM_CODEGEN_TARGETLOWERINGOBJECTFILE_H
+#define LLVM_CODEGEN_TARGETLOWERINGOBJECTFILE_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringRef.h"
@@ -191,4 +191,4 @@ protected:
} // end namespace llvm
-#endif // LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
+#endif // LLVM_CODEGEN_TARGETLOWERINGOBJECTFILE_H
Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Thu Nov 16 17:07:10 2017
@@ -15,9 +15,9 @@
#ifndef LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H
#define LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCExpr.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
namespace llvm {
Copied: llvm/trunk/include/llvm/CodeGen/TargetOpcodes.def (from r318489, llvm/trunk/include/llvm/Target/TargetOpcodes.def)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetOpcodes.def?p2=llvm/trunk/include/llvm/CodeGen/TargetOpcodes.def&p1=llvm/trunk/include/llvm/Target/TargetOpcodes.def&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetOpcodes.def Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===//
+//===-- llvm/CodeGen/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
Copied: llvm/trunk/include/llvm/CodeGen/TargetOpcodes.h (from r318489, llvm/trunk/include/llvm/Target/TargetOpcodes.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetOpcodes.h?p2=llvm/trunk/include/llvm/CodeGen/TargetOpcodes.h&p1=llvm/trunk/include/llvm/Target/TargetOpcodes.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetOpcodes.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===//
+//===-- llvm/CodeGen/TargetOpcodes.h - Target Indep Opcodes -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETOPCODES_H
-#define LLVM_TARGET_TARGETOPCODES_H
+#ifndef LLVM_CODEGEN_TARGETOPCODES_H
+#define LLVM_CODEGEN_TARGETOPCODES_H
namespace llvm {
@@ -22,7 +22,7 @@ namespace TargetOpcode {
enum {
#define HANDLE_TARGET_OPCODE(OPC) OPC,
#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
-#include "llvm/Target/TargetOpcodes.def"
+#include "llvm/CodeGen/TargetOpcodes.def"
};
} // end namespace TargetOpcode
Copied: llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h (from r318489, llvm/trunk/include/llvm/Target/TargetRegisterInfo.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h?p2=llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h&p1=llvm/trunk/include/llvm/Target/TargetRegisterInfo.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//==- Target/TargetRegisterInfo.h - Target Register Information --*- C++ -*-==//
+//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@@ -13,8 +13,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
-#define LLVM_TARGET_TARGETREGISTERINFO_H
+#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
+#define LLVM_CODEGEN_TARGETREGISTERINFO_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
@@ -1163,4 +1163,4 @@ Printable PrintVRegOrUnit(unsigned VRegO
} // end namespace llvm
-#endif // LLVM_TARGET_TARGETREGISTERINFO_H
+#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
Modified: llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSchedule.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSchedule.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSchedule.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
namespace llvm {
Copied: llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h (from r318489, llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h?p2=llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h&p1=llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h&r1=318489&r2=318490&rev=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h Thu Nov 16 17:07:10 2017
@@ -1,4 +1,4 @@
-//===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===//
+//===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
-#define LLVM_TARGET_TARGETSUBTARGETINFO_H
+#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
+#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
@@ -252,4 +252,4 @@ public:
} // end namespace llvm
-#endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
+#endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
Modified: llvm/trunk/include/llvm/CodeGen/VirtRegMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/VirtRegMap.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/VirtRegMap.h (original)
+++ llvm/trunk/include/llvm/CodeGen/VirtRegMap.h Thu Nov 16 17:07:10 2017
@@ -19,9 +19,9 @@
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
namespace llvm {
Removed: llvm/trunk/include/llvm/Target/CostTable.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/CostTable.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/CostTable.h (original)
+++ llvm/trunk/include/llvm/Target/CostTable.h (removed)
@@ -1,70 +0,0 @@
-//===-- CostTable.h - Instruction Cost Table handling -----------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-///
-/// \file
-/// \brief Cost tables and simple lookup functions
-///
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_COSTTABLE_H_
-#define LLVM_TARGET_COSTTABLE_H_
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/CodeGen/MachineValueType.h"
-
-namespace llvm {
-
-/// Cost Table Entry
-struct CostTblEntry {
- int ISD;
- MVT::SimpleValueType Type;
- unsigned Cost;
-};
-
-/// Find in cost table, TypeTy must be comparable to CompareTy by ==
-inline const CostTblEntry *CostTableLookup(ArrayRef<CostTblEntry> Tbl,
- int ISD, MVT Ty) {
- auto I = find_if(Tbl, [=](const CostTblEntry &Entry) {
- return ISD == Entry.ISD && Ty == Entry.Type;
- });
- if (I != Tbl.end())
- return I;
-
- // Could not find an entry.
- return nullptr;
-}
-
-/// Type Conversion Cost Table
-struct TypeConversionCostTblEntry {
- int ISD;
- MVT::SimpleValueType Dst;
- MVT::SimpleValueType Src;
- unsigned Cost;
-};
-
-/// Find in type conversion cost table, TypeTy must be comparable to CompareTy
-/// by ==
-inline const TypeConversionCostTblEntry *
-ConvertCostTableLookup(ArrayRef<TypeConversionCostTblEntry> Tbl,
- int ISD, MVT Dst, MVT Src) {
- auto I = find_if(Tbl, [=](const TypeConversionCostTblEntry &Entry) {
- return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
- });
- if (I != Tbl.end())
- return I;
-
- // Could not find an entry.
- return nullptr;
-}
-
-} // namespace llvm
-
-
-#endif /* LLVM_TARGET_COSTTABLE_H_ */
Removed: llvm/trunk/include/llvm/Target/TargetCallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetCallingConv.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetCallingConv.h (original)
+++ llvm/trunk/include/llvm/Target/TargetCallingConv.h (removed)
@@ -1,204 +0,0 @@
-//===-- llvm/Target/TargetCallingConv.h - Calling Convention ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines types for working with calling-convention information.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
-#define LLVM_TARGET_TARGETCALLINGCONV_H
-
-#include "llvm/CodeGen/MachineValueType.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Support/MathExtras.h"
-#include <cassert>
-#include <climits>
-#include <cstdint>
-
-namespace llvm {
-namespace ISD {
-
- struct ArgFlagsTy {
- private:
- unsigned IsZExt : 1; ///< Zero extended
- unsigned IsSExt : 1; ///< Sign extended
- unsigned IsInReg : 1; ///< Passed in register
- unsigned IsSRet : 1; ///< Hidden struct-ret ptr
- unsigned IsByVal : 1; ///< Struct passed by value
- unsigned IsNest : 1; ///< Nested fn static chain
- unsigned IsReturned : 1; ///< Always returned
- unsigned IsSplit : 1;
- unsigned IsInAlloca : 1; ///< Passed with inalloca
- unsigned IsSplitEnd : 1; ///< Last part of a split
- unsigned IsSwiftSelf : 1; ///< Swift self parameter
- unsigned IsSwiftError : 1; ///< Swift error parameter
- unsigned IsHva : 1; ///< HVA field for
- unsigned IsHvaStart : 1; ///< HVA structure start
- unsigned IsSecArgPass : 1; ///< Second argument
- unsigned ByValAlign : 4; ///< Log 2 of byval alignment
- unsigned OrigAlign : 5; ///< Log 2 of original alignment
- unsigned IsInConsecutiveRegsLast : 1;
- unsigned IsInConsecutiveRegs : 1;
- unsigned IsCopyElisionCandidate : 1; ///< Argument copy elision candidate
-
- unsigned ByValSize; ///< Byval struct size
-
- public:
- ArgFlagsTy()
- : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsNest(0),
- IsReturned(0), IsSplit(0), IsInAlloca(0), IsSplitEnd(0),
- IsSwiftSelf(0), IsSwiftError(0), IsHva(0), IsHvaStart(0),
- IsSecArgPass(0), ByValAlign(0), OrigAlign(0),
- IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0),
- IsCopyElisionCandidate(0), ByValSize(0) {
- static_assert(sizeof(*this) == 2 * sizeof(unsigned), "flags are too big");
- }
-
- bool isZExt() const { return IsZExt; }
- void setZExt() { IsZExt = 1; }
-
- bool isSExt() const { return IsSExt; }
- void setSExt() { IsSExt = 1; }
-
- bool isInReg() const { return IsInReg; }
- void setInReg() { IsInReg = 1; }
-
- bool isSRet() const { return IsSRet; }
- void setSRet() { IsSRet = 1; }
-
- bool isByVal() const { return IsByVal; }
- void setByVal() { IsByVal = 1; }
-
- bool isInAlloca() const { return IsInAlloca; }
- void setInAlloca() { IsInAlloca = 1; }
-
- bool isSwiftSelf() const { return IsSwiftSelf; }
- void setSwiftSelf() { IsSwiftSelf = 1; }
-
- bool isSwiftError() const { return IsSwiftError; }
- void setSwiftError() { IsSwiftError = 1; }
-
- bool isHva() const { return IsHva; }
- void setHva() { IsHva = 1; }
-
- bool isHvaStart() const { return IsHvaStart; }
- void setHvaStart() { IsHvaStart = 1; }
-
- bool isSecArgPass() const { return IsSecArgPass; }
- void setSecArgPass() { IsSecArgPass = 1; }
-
- bool isNest() const { return IsNest; }
- void setNest() { IsNest = 1; }
-
- bool isReturned() const { return IsReturned; }
- void setReturned() { IsReturned = 1; }
-
- bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; }
- void setInConsecutiveRegs() { IsInConsecutiveRegs = 1; }
-
- bool isInConsecutiveRegsLast() const { return IsInConsecutiveRegsLast; }
- void setInConsecutiveRegsLast() { IsInConsecutiveRegsLast = 1; }
-
- bool isSplit() const { return IsSplit; }
- void setSplit() { IsSplit = 1; }
-
- bool isSplitEnd() const { return IsSplitEnd; }
- void setSplitEnd() { IsSplitEnd = 1; }
-
- bool isCopyElisionCandidate() const { return IsCopyElisionCandidate; }
- void setCopyElisionCandidate() { IsCopyElisionCandidate = 1; }
-
- unsigned getByValAlign() const { return (1U << ByValAlign) / 2; }
- void setByValAlign(unsigned A) {
- ByValAlign = Log2_32(A) + 1;
- assert(getByValAlign() == A && "bitfield overflow");
- }
-
- unsigned getOrigAlign() const { return (1U << OrigAlign) / 2; }
- void setOrigAlign(unsigned A) {
- OrigAlign = Log2_32(A) + 1;
- assert(getOrigAlign() == A && "bitfield overflow");
- }
-
- unsigned getByValSize() const { return ByValSize; }
- void setByValSize(unsigned S) { ByValSize = S; }
- };
-
- /// InputArg - This struct carries flags and type information about a
- /// single incoming (formal) argument or incoming (from the perspective
- /// of the caller) return value virtual register.
- ///
- struct InputArg {
- ArgFlagsTy Flags;
- MVT VT = MVT::Other;
- EVT ArgVT;
- bool Used = false;
-
- /// Index original Function's argument.
- unsigned OrigArgIndex;
- /// Sentinel value for implicit machine-level input arguments.
- static const unsigned NoArgIndex = UINT_MAX;
-
- /// Offset in bytes of current input value relative to the beginning of
- /// original argument. E.g. if argument was splitted into four 32 bit
- /// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
- unsigned PartOffset;
-
- InputArg() = default;
- InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
- unsigned origIdx, unsigned partOffs)
- : Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOffs) {
- VT = vt.getSimpleVT();
- ArgVT = argvt;
- }
-
- bool isOrigArg() const {
- return OrigArgIndex != NoArgIndex;
- }
-
- unsigned getOrigArgIndex() const {
- assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument");
- return OrigArgIndex;
- }
- };
-
- /// OutputArg - This struct carries flags and a value for a
- /// single outgoing (actual) argument or outgoing (from the perspective
- /// of the caller) return value virtual register.
- ///
- struct OutputArg {
- ArgFlagsTy Flags;
- MVT VT;
- EVT ArgVT;
-
- /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
- bool IsFixed = false;
-
- /// Index original Function's argument.
- unsigned OrigArgIndex;
-
- /// Offset in bytes of current output value relative to the beginning of
- /// original argument. E.g. if argument was splitted into four 32 bit
- /// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
- unsigned PartOffset;
-
- OutputArg() = default;
- OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed,
- unsigned origIdx, unsigned partOffs)
- : Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
- PartOffset(partOffs) {
- VT = vt.getSimpleVT();
- ArgVT = argvt;
- }
- };
-
-} // end namespace ISD
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETCALLINGCONV_H
Removed: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h (removed)
@@ -1,3515 +0,0 @@
-//===- llvm/Target/TargetLowering.h - Target Lowering Info ------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-///
-/// \file
-/// This file describes how to lower LLVM code to machine code. This has two
-/// main components:
-///
-/// 1. Which ValueTypes are natively supported by the target.
-/// 2. Which operations are supported for supported ValueTypes.
-/// 3. Cost thresholds for alternative implementations of certain operations.
-///
-/// In addition it has a few other components, like information about FP
-/// immediates.
-///
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETLOWERING_H
-#define LLVM_TARGET_TARGETLOWERING_H
-
-#include "llvm/ADT/APInt.h"
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/DAGCombine.h"
-#include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/CodeGen/MachineValueType.h"
-#include "llvm/CodeGen/RuntimeLibcalls.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/IR/Attributes.h"
-#include "llvm/IR/CallSite.h"
-#include "llvm/IR/CallingConv.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/IR/DerivedTypes.h"
-#include "llvm/IR/Function.h"
-#include "llvm/IR/IRBuilder.h"
-#include "llvm/IR/InlineAsm.h"
-#include "llvm/IR/Instruction.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/Type.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Support/AtomicOrdering.h"
-#include "llvm/Support/Casting.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetCallingConv.h"
-#include "llvm/Target/TargetMachine.h"
-#include <algorithm>
-#include <cassert>
-#include <climits>
-#include <cstdint>
-#include <iterator>
-#include <map>
-#include <string>
-#include <utility>
-#include <vector>
-
-namespace llvm {
-
-class BranchProbability;
-class CCState;
-class CCValAssign;
-class Constant;
-class FastISel;
-class FunctionLoweringInfo;
-class GlobalValue;
-class IntrinsicInst;
-struct KnownBits;
-class LLVMContext;
-class MachineBasicBlock;
-class MachineFunction;
-class MachineInstr;
-class MachineJumpTableInfo;
-class MachineLoop;
-class MachineRegisterInfo;
-class MCContext;
-class MCExpr;
-class Module;
-class TargetRegisterClass;
-class TargetLibraryInfo;
-class TargetRegisterInfo;
-class Value;
-
-namespace Sched {
-
- enum Preference {
- None, // No preference
- Source, // Follow source order.
- RegPressure, // Scheduling for lowest register pressure.
- Hybrid, // Scheduling for both latency and register pressure.
- ILP, // Scheduling for ILP in low register pressure mode.
- VLIW // Scheduling for VLIW targets.
- };
-
-} // end namespace Sched
-
-/// This base class for TargetLowering contains the SelectionDAG-independent
-/// parts that can be used from the rest of CodeGen.
-class TargetLoweringBase {
-public:
- /// This enum indicates whether operations are valid for a target, and if not,
- /// what action should be used to make them valid.
- enum LegalizeAction : uint8_t {
- Legal, // The target natively supports this operation.
- Promote, // This operation should be executed in a larger type.
- Expand, // Try to expand this to other ops, otherwise use a libcall.
- LibCall, // Don't try to expand this to other ops, always use a libcall.
- Custom // Use the LowerOperation hook to implement custom lowering.
- };
-
- /// This enum indicates whether a types are legal for a target, and if not,
- /// what action should be used to make them valid.
- enum LegalizeTypeAction : uint8_t {
- TypeLegal, // The target natively supports this type.
- TypePromoteInteger, // Replace this integer with a larger one.
- TypeExpandInteger, // Split this integer into two of half the size.
- TypeSoftenFloat, // Convert this float to a same size integer type,
- // if an operation is not supported in target HW.
- TypeExpandFloat, // Split this float into two of half the size.
- TypeScalarizeVector, // Replace this one-element vector with its element.
- TypeSplitVector, // Split this vector into two of half the size.
- TypeWidenVector, // This vector should be widened into a larger vector.
- TypePromoteFloat // Replace this float with a larger one.
- };
-
- /// LegalizeKind holds the legalization kind that needs to happen to EVT
- /// in order to type-legalize it.
- using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
-
- /// Enum that describes how the target represents true/false values.
- enum BooleanContent {
- UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
- ZeroOrOneBooleanContent, // All bits zero except for bit 0.
- ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
- };
-
- /// Enum that describes what type of support for selects the target has.
- enum SelectSupportKind {
- ScalarValSelect, // The target supports scalar selects (ex: cmov).
- ScalarCondVectorVal, // The target supports selects with a scalar condition
- // and vector values (ex: cmov).
- VectorMaskSelect // The target supports vector selects with a vector
- // mask (ex: x86 blends).
- };
-
- /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
- /// to, if at all. Exists because different targets have different levels of
- /// support for these atomic instructions, and also have different options
- /// w.r.t. what they should expand to.
- enum class AtomicExpansionKind {
- None, // Don't expand the instruction.
- LLSC, // Expand the instruction into loadlinked/storeconditional; used
- // by ARM/AArch64.
- LLOnly, // Expand the (load) instruction into just a load-linked, which has
- // greater atomic guarantees than a normal load.
- CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
- };
-
- /// Enum that specifies when a multiplication should be expanded.
- enum class MulExpansionKind {
- Always, // Always expand the instruction.
- OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
- // or custom.
- };
-
- class ArgListEntry {
- public:
- Value *Val = nullptr;
- SDValue Node = SDValue();
- Type *Ty = nullptr;
- bool IsSExt : 1;
- bool IsZExt : 1;
- bool IsInReg : 1;
- bool IsSRet : 1;
- bool IsNest : 1;
- bool IsByVal : 1;
- bool IsInAlloca : 1;
- bool IsReturned : 1;
- bool IsSwiftSelf : 1;
- bool IsSwiftError : 1;
- uint16_t Alignment = 0;
-
- ArgListEntry()
- : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
- IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
- IsSwiftSelf(false), IsSwiftError(false) {}
-
- void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
- };
- using ArgListTy = std::vector<ArgListEntry>;
-
- virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
- ArgListTy &Args) const {};
-
- static ISD::NodeType getExtendForContent(BooleanContent Content) {
- switch (Content) {
- case UndefinedBooleanContent:
- // Extend by adding rubbish bits.
- return ISD::ANY_EXTEND;
- case ZeroOrOneBooleanContent:
- // Extend by adding zero bits.
- return ISD::ZERO_EXTEND;
- case ZeroOrNegativeOneBooleanContent:
- // Extend by copying the sign bit.
- return ISD::SIGN_EXTEND;
- }
- llvm_unreachable("Invalid content kind");
- }
-
- /// NOTE: The TargetMachine owns TLOF.
- explicit TargetLoweringBase(const TargetMachine &TM);
- TargetLoweringBase(const TargetLoweringBase &) = delete;
- TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
- virtual ~TargetLoweringBase() = default;
-
-protected:
- /// \brief Initialize all of the actions to default values.
- void initActions();
-
-public:
- const TargetMachine &getTargetMachine() const { return TM; }
-
- virtual bool useSoftFloat() const { return false; }
-
- /// Return the pointer type for the given address space, defaults to
- /// the pointer type from the data layout.
- /// FIXME: The default needs to be removed once all the code is updated.
- MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
- return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
- }
-
- /// Return the type for frame index, which is determined by
- /// the alloca address space specified through the data layout.
- MVT getFrameIndexTy(const DataLayout &DL) const {
- return getPointerTy(DL, DL.getAllocaAddrSpace());
- }
-
- /// Return the type for operands of fence.
- /// TODO: Let fence operands be of i32 type and remove this.
- virtual MVT getFenceOperandTy(const DataLayout &DL) const {
- return getPointerTy(DL);
- }
-
- /// EVT is not used in-tree, but is used by out-of-tree target.
- /// A documentation for this function would be nice...
- virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
-
- EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
-
- /// Returns the type to be used for the index operand of:
- /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
- /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
- virtual MVT getVectorIdxTy(const DataLayout &DL) const {
- return getPointerTy(DL);
- }
-
- virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
- return true;
- }
-
- /// Return true if multiple condition registers are available.
- bool hasMultipleConditionRegisters() const {
- return HasMultipleConditionRegisters;
- }
-
- /// Return true if the target has BitExtract instructions.
- bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
-
- /// Return the preferred vector type legalization action.
- virtual TargetLoweringBase::LegalizeTypeAction
- getPreferredVectorAction(EVT VT) const {
- // The default action for one element vectors is to scalarize
- if (VT.getVectorNumElements() == 1)
- return TypeScalarizeVector;
- // The default action for other vectors is to promote
- return TypePromoteInteger;
- }
-
- // There are two general methods for expanding a BUILD_VECTOR node:
- // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
- // them together.
- // 2. Build the vector on the stack and then load it.
- // If this function returns true, then method (1) will be used, subject to
- // the constraint that all of the necessary shuffles are legal (as determined
- // by isShuffleMaskLegal). If this function returns false, then method (2) is
- // always used. The vector type, and the number of defined values, are
- // provided.
- virtual bool
- shouldExpandBuildVectorWithShuffles(EVT /* VT */,
- unsigned DefinedValues) const {
- return DefinedValues < 3;
- }
-
- /// Return true if integer divide is usually cheaper than a sequence of
- /// several shifts, adds, and multiplies for this target.
- /// The definition of "cheaper" may depend on whether we're optimizing
- /// for speed or for size.
- virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
-
- /// Return true if the target can handle a standalone remainder operation.
- virtual bool hasStandaloneRem(EVT VT) const {
- return true;
- }
-
- /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
- virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
- // Default behavior is to replace SQRT(X) with X*RSQRT(X).
- return false;
- }
-
- /// Reciprocal estimate status values used by the functions below.
- enum ReciprocalEstimate : int {
- Unspecified = -1,
- Disabled = 0,
- Enabled = 1
- };
-
- /// Return a ReciprocalEstimate enum value for a square root of the given type
- /// based on the function's attributes. If the operation is not overridden by
- /// the function's attributes, "Unspecified" is returned and target defaults
- /// are expected to be used for instruction selection.
- int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
-
- /// Return a ReciprocalEstimate enum value for a division of the given type
- /// based on the function's attributes. If the operation is not overridden by
- /// the function's attributes, "Unspecified" is returned and target defaults
- /// are expected to be used for instruction selection.
- int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
-
- /// Return the refinement step count for a square root of the given type based
- /// on the function's attributes. If the operation is not overridden by
- /// the function's attributes, "Unspecified" is returned and target defaults
- /// are expected to be used for instruction selection.
- int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
-
- /// Return the refinement step count for a division of the given type based
- /// on the function's attributes. If the operation is not overridden by
- /// the function's attributes, "Unspecified" is returned and target defaults
- /// are expected to be used for instruction selection.
- int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
-
- /// Returns true if target has indicated at least one type should be bypassed.
- bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
-
- /// Returns map of slow types for division or remainder with corresponding
- /// fast types
- const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
- return BypassSlowDivWidths;
- }
-
- /// Return true if Flow Control is an expensive operation that should be
- /// avoided.
- bool isJumpExpensive() const { return JumpIsExpensive; }
-
- /// Return true if selects are only cheaper than branches if the branch is
- /// unlikely to be predicted right.
- bool isPredictableSelectExpensive() const {
- return PredictableSelectIsExpensive;
- }
-
- /// If a branch or a select condition is skewed in one direction by more than
- /// this factor, it is very likely to be predicted correctly.
- virtual BranchProbability getPredictableBranchThreshold() const;
-
- /// Return true if the following transform is beneficial:
- /// fold (conv (load x)) -> (load (conv*)x)
- /// On architectures that don't natively support some vector loads
- /// efficiently, casting the load to a smaller vector of larger types and
- /// loading is more efficient, however, this can be undone by optimizations in
- /// dag combiner.
- virtual bool isLoadBitCastBeneficial(EVT LoadVT,
- EVT BitcastVT) const {
- // Don't do if we could do an indexed load on the original type, but not on
- // the new one.
- if (!LoadVT.isSimple() || !BitcastVT.isSimple())
- return true;
-
- MVT LoadMVT = LoadVT.getSimpleVT();
-
- // Don't bother doing this if it's just going to be promoted again later, as
- // doing so might interfere with other combines.
- if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
- getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
- return false;
-
- return true;
- }
-
- /// Return true if the following transform is beneficial:
- /// (store (y (conv x)), y*)) -> (store x, (x*))
- virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
- // Default to the same logic as loads.
- return isLoadBitCastBeneficial(StoreVT, BitcastVT);
- }
-
- /// Return true if it is expected to be cheaper to do a store of a non-zero
- /// vector constant with the given size and type for the address space than to
- /// store the individual scalar element constants.
- virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
- unsigned NumElem,
- unsigned AddrSpace) const {
- return false;
- }
-
- /// Allow store merging after legalization in addition to before legalization.
- /// This may catch stores that do not exist earlier (eg, stores created from
- /// intrinsics).
- virtual bool mergeStoresAfterLegalization() const { return false; }
-
- /// Returns if it's reasonable to merge stores to MemVT size.
- virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
- const SelectionDAG &DAG) const {
- return true;
- }
-
- /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
- virtual bool isCheapToSpeculateCttz() const {
- return false;
- }
-
- /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
- virtual bool isCheapToSpeculateCtlz() const {
- return false;
- }
-
- /// \brief Return true if ctlz instruction is fast.
- virtual bool isCtlzFast() const {
- return false;
- }
-
- /// Return true if it is safe to transform an integer-domain bitwise operation
- /// into the equivalent floating-point operation. This should be set to true
- /// if the target has IEEE-754-compliant fabs/fneg operations for the input
- /// type.
- virtual bool hasBitPreservingFPLogic(EVT VT) const {
- return false;
- }
-
- /// \brief Return true if it is cheaper to split the store of a merged int val
- /// from a pair of smaller values into multiple stores.
- virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
- return false;
- }
-
- /// \brief Return if the target supports combining a
- /// chain like:
- /// \code
- /// %andResult = and %val1, #mask
- /// %icmpResult = icmp %andResult, 0
- /// \endcode
- /// into a single machine instruction of a form like:
- /// \code
- /// cc = test %register, #mask
- /// \endcode
- virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
- return false;
- }
-
- /// Use bitwise logic to make pairs of compares more efficient. For example:
- /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
- /// This should be true when it takes more than one instruction to lower
- /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
- /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
- virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
- return false;
- }
-
- /// Return the preferred operand type if the target has a quick way to compare
- /// integer values of the given size. Assume that any legal integer type can
- /// be compared efficiently. Targets may override this to allow illegal wide
- /// types to return a vector type if there is support to compare that type.
- virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
- MVT VT = MVT::getIntegerVT(NumBits);
- return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
- }
-
- /// Return true if the target should transform:
- /// (X & Y) == Y ---> (~X & Y) == 0
- /// (X & Y) != Y ---> (~X & Y) != 0
- ///
- /// This may be profitable if the target has a bitwise and-not operation that
- /// sets comparison flags. A target may want to limit the transformation based
- /// on the type of Y or if Y is a constant.
- ///
- /// Note that the transform will not occur if Y is known to be a power-of-2
- /// because a mask and compare of a single bit can be handled by inverting the
- /// predicate, for example:
- /// (X & 8) == 8 ---> (X & 8) != 0
- virtual bool hasAndNotCompare(SDValue Y) const {
- return false;
- }
-
- /// Return true if the target has a bitwise and-not operation:
- /// X = ~A & B
- /// This can be used to simplify select or other instructions.
- virtual bool hasAndNot(SDValue X) const {
- // If the target has the more complex version of this operation, assume that
- // it has this operation too.
- return hasAndNotCompare(X);
- }
-
- /// \brief Return true if the target wants to use the optimization that
- /// turns ext(promotableInst1(...(promotableInstN(load)))) into
- /// promotedInst1(...(promotedInstN(ext(load)))).
- bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
-
- /// Return true if the target can combine store(extractelement VectorTy,
- /// Idx).
- /// \p Cost[out] gives the cost of that transformation when this is true.
- virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
- unsigned &Cost) const {
- return false;
- }
-
- /// Return true if target supports floating point exceptions.
- bool hasFloatingPointExceptions() const {
- return HasFloatingPointExceptions;
- }
-
- /// Return true if target always beneficiates from combining into FMA for a
- /// given value type. This must typically return false on targets where FMA
- /// takes more cycles to execute than FADD.
- virtual bool enableAggressiveFMAFusion(EVT VT) const {
- return false;
- }
-
- /// Return the ValueType of the result of SETCC operations.
- virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
- EVT VT) const;
-
- /// Return the ValueType for comparison libcalls. Comparions libcalls include
- /// floating point comparion calls, and Ordered/Unordered check calls on
- /// floating point numbers.
- virtual
- MVT::SimpleValueType getCmpLibcallReturnType() const;
-
- /// For targets without i1 registers, this gives the nature of the high-bits
- /// of boolean values held in types wider than i1.
- ///
- /// "Boolean values" are special true/false values produced by nodes like
- /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
- /// Not to be confused with general values promoted from i1. Some cpus
- /// distinguish between vectors of boolean and scalars; the isVec parameter
- /// selects between the two kinds. For example on X86 a scalar boolean should
- /// be zero extended from i1, while the elements of a vector of booleans
- /// should be sign extended from i1.
- ///
- /// Some cpus also treat floating point types the same way as they treat
- /// vectors instead of the way they treat scalars.
- BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
- if (isVec)
- return BooleanVectorContents;
- return isFloat ? BooleanFloatContents : BooleanContents;
- }
-
- BooleanContent getBooleanContents(EVT Type) const {
- return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
- }
-
- /// Return target scheduling preference.
- Sched::Preference getSchedulingPreference() const {
- return SchedPreferenceInfo;
- }
-
- /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
- /// for different nodes. This function returns the preference (or none) for
- /// the given node.
- virtual Sched::Preference getSchedulingPreference(SDNode *) const {
- return Sched::None;
- }
-
- /// Return the register class that should be used for the specified value
- /// type.
- virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
- const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
- assert(RC && "This value type is not natively supported!");
- return RC;
- }
-
- /// Return the 'representative' register class for the specified value
- /// type.
- ///
- /// The 'representative' register class is the largest legal super-reg
- /// register class for the register class of the value type. For example, on
- /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
- /// register class is GR64 on x86_64.
- virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
- const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
- return RC;
- }
-
- /// Return the cost of the 'representative' register class for the specified
- /// value type.
- virtual uint8_t getRepRegClassCostFor(MVT VT) const {
- return RepRegClassCostForVT[VT.SimpleTy];
- }
-
- /// Return true if the target has native support for the specified value type.
- /// This means that it has a register that directly holds it without
- /// promotions or expansions.
- bool isTypeLegal(EVT VT) const {
- assert(!VT.isSimple() ||
- (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
- return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
- }
-
- class ValueTypeActionImpl {
- /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
- /// that indicates how instruction selection should deal with the type.
- LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
-
- public:
- ValueTypeActionImpl() {
- std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
- TypeLegal);
- }
-
- LegalizeTypeAction getTypeAction(MVT VT) const {
- return ValueTypeActions[VT.SimpleTy];
- }
-
- void setTypeAction(MVT VT, LegalizeTypeAction Action) {
- ValueTypeActions[VT.SimpleTy] = Action;
- }
- };
-
- const ValueTypeActionImpl &getValueTypeActions() const {
- return ValueTypeActions;
- }
-
- /// Return how we should legalize values of this type, either it is already
- /// legal (return 'Legal') or we need to promote it to a larger type (return
- /// 'Promote'), or we need to expand it into multiple registers of smaller
- /// integer type (return 'Expand'). 'Custom' is not an option.
- LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
- return getTypeConversion(Context, VT).first;
- }
- LegalizeTypeAction getTypeAction(MVT VT) const {
- return ValueTypeActions.getTypeAction(VT);
- }
-
- /// For types supported by the target, this is an identity function. For
- /// types that must be promoted to larger types, this returns the larger type
- /// to promote to. For integer types that are larger than the largest integer
- /// register, this contains one step in the expansion to get to the smaller
- /// register. For illegal floating point types, this returns the integer type
- /// to transform to.
- EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
- return getTypeConversion(Context, VT).second;
- }
-
- /// For types supported by the target, this is an identity function. For
- /// types that must be expanded (i.e. integer types that are larger than the
- /// largest integer register or illegal floating point types), this returns
- /// the largest legal type it will be expanded to.
- EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
- assert(!VT.isVector());
- while (true) {
- switch (getTypeAction(Context, VT)) {
- case TypeLegal:
- return VT;
- case TypeExpandInteger:
- VT = getTypeToTransformTo(Context, VT);
- break;
- default:
- llvm_unreachable("Type is not legal nor is it to be expanded!");
- }
- }
- }
-
- /// Vector types are broken down into some number of legal first class types.
- /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
- /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
- /// turns into 4 EVT::i32 values with both PPC and X86.
- ///
- /// This method returns the number of registers needed, and the VT for each
- /// register. It also returns the VT and quantity of the intermediate values
- /// before they are promoted/expanded.
- unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
- EVT &IntermediateVT,
- unsigned &NumIntermediates,
- MVT &RegisterVT) const;
-
- /// Certain targets such as MIPS require that some types such as vectors are
- /// always broken down into scalars in some contexts. This occurs even if the
- /// vector type is legal.
- virtual unsigned getVectorTypeBreakdownForCallingConv(
- LLVMContext &Context, EVT VT, EVT &IntermediateVT,
- unsigned &NumIntermediates, MVT &RegisterVT) const {
- return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
- RegisterVT);
- }
-
- struct IntrinsicInfo {
- unsigned opc = 0; // target opcode
- EVT memVT; // memory VT
- const Value* ptrVal = nullptr; // value representing memory location
- int offset = 0; // offset off of ptrVal
- unsigned size = 0; // the size of the memory location
- // (taken from memVT if zero)
- unsigned align = 1; // alignment
- bool vol = false; // is volatile?
- bool readMem = false; // reads memory?
- bool writeMem = false; // writes memory?
-
- IntrinsicInfo() = default;
- };
-
- /// Given an intrinsic, checks if on the target the intrinsic will need to map
- /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
- /// true and store the intrinsic information into the IntrinsicInfo that was
- /// passed to the function.
- virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
- unsigned /*Intrinsic*/) const {
- return false;
- }
-
- /// Returns true if the target can instruction select the specified FP
- /// immediate natively. If false, the legalizer will materialize the FP
- /// immediate as a load from a constant pool.
- virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
- return false;
- }
-
- /// Targets can use this to indicate that they only support *some*
- /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
- /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
- /// legal.
- virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
- return true;
- }
-
- /// Returns true if the operation can trap for the value type.
- ///
- /// VT must be a legal type. By default, we optimistically assume most
- /// operations don't trap except for integer divide and remainder.
- virtual bool canOpTrap(unsigned Op, EVT VT) const;
-
- /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
- /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
- /// a VAND with a constant pool entry.
- virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
- EVT /*VT*/) const {
- return false;
- }
-
- /// Return how this operation should be treated: either it is legal, needs to
- /// be promoted to a larger size, needs to be expanded to some other code
- /// sequence, or the target has a custom expander for it.
- LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
- if (VT.isExtended()) return Expand;
- // If a target-specific SDNode requires legalization, require the target
- // to provide custom legalization for it.
- if (Op >= array_lengthof(OpActions[0])) return Custom;
- return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
- }
-
- /// Return true if the specified operation is legal on this target or can be
- /// made legal with custom lowering. This is used to help guide high-level
- /// lowering decisions.
- bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Custom);
- }
-
- /// Return true if the specified operation is legal on this target or can be
- /// made legal using promotion. This is used to help guide high-level lowering
- /// decisions.
- bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Promote);
- }
-
- /// Return true if the specified operation is legal on this target or can be
- /// made legal with custom lowering or using promotion. This is used to help
- /// guide high-level lowering decisions.
- bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Custom ||
- getOperationAction(Op, VT) == Promote);
- }
-
- /// Return true if the operation uses custom lowering, regardless of whether
- /// the type is legal or not.
- bool isOperationCustom(unsigned Op, EVT VT) const {
- return getOperationAction(Op, VT) == Custom;
- }
-
- /// Return true if lowering to a jump table is allowed.
- bool areJTsAllowed(const Function *Fn) const {
- if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
- return false;
-
- return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
- isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
- }
-
- /// Check whether the range [Low,High] fits in a machine word.
- bool rangeFitsInWord(const APInt &Low, const APInt &High,
- const DataLayout &DL) const {
- // FIXME: Using the pointer type doesn't seem ideal.
- uint64_t BW = DL.getPointerSizeInBits();
- uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
- return Range <= BW;
- }
-
- /// Return true if lowering to a jump table is suitable for a set of case
- /// clusters which may contain \p NumCases cases, \p Range range of values.
- /// FIXME: This function check the maximum table size and density, but the
- /// minimum size is not checked. It would be nice if the the minimum size is
- /// also combined within this function. Currently, the minimum size check is
- /// performed in findJumpTable() in SelectionDAGBuiler and
- /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
- bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
- uint64_t Range) const {
- const bool OptForSize = SI->getParent()->getParent()->optForSize();
- const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
- const unsigned MaxJumpTableSize =
- OptForSize || getMaximumJumpTableSize() == 0
- ? UINT_MAX
- : getMaximumJumpTableSize();
- // Check whether a range of clusters is dense enough for a jump table.
- if (Range <= MaxJumpTableSize &&
- (NumCases * 100 >= Range * MinDensity)) {
- return true;
- }
- return false;
- }
-
- /// Return true if lowering to a bit test is suitable for a set of case
- /// clusters which contains \p NumDests unique destinations, \p Low and
- /// \p High as its lowest and highest case values, and expects \p NumCmps
- /// case value comparisons. Check if the number of destinations, comparison
- /// metric, and range are all suitable.
- bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
- const APInt &Low, const APInt &High,
- const DataLayout &DL) const {
- // FIXME: I don't think NumCmps is the correct metric: a single case and a
- // range of cases both require only one branch to lower. Just looking at the
- // number of clusters and destinations should be enough to decide whether to
- // build bit tests.
-
- // To lower a range with bit tests, the range must fit the bitwidth of a
- // machine word.
- if (!rangeFitsInWord(Low, High, DL))
- return false;
-
- // Decide whether it's profitable to lower this range with bit tests. Each
- // destination requires a bit test and branch, and there is an overall range
- // check branch. For a small number of clusters, separate comparisons might
- // be cheaper, and for many destinations, splitting the range might be
- // better.
- return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
- (NumDests == 3 && NumCmps >= 6);
- }
-
- /// Return true if the specified operation is illegal on this target or
- /// unlikely to be made legal with custom lowering. This is used to help guide
- /// high-level lowering decisions.
- bool isOperationExpand(unsigned Op, EVT VT) const {
- return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
- }
-
- /// Return true if the specified operation is legal on this target.
- bool isOperationLegal(unsigned Op, EVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- getOperationAction(Op, VT) == Legal;
- }
-
- /// Return how this load with extension should be treated: either it is legal,
- /// needs to be promoted to a larger size, needs to be expanded to some other
- /// code sequence, or the target has a custom expander for it.
- LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
- EVT MemVT) const {
- if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
- unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
- unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
- assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
- MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
- unsigned Shift = 4 * ExtType;
- return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
- }
-
- /// Return true if the specified load with extension is legal on this target.
- bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
- return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
- }
-
- /// Return true if the specified load with extension is legal or custom
- /// on this target.
- bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
- return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
- getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
- }
-
- /// Return how this store with truncation should be treated: either it is
- /// legal, needs to be promoted to a larger size, needs to be expanded to some
- /// other code sequence, or the target has a custom expander for it.
- LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
- if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
- unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
- unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
- assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
- "Table isn't big enough!");
- return TruncStoreActions[ValI][MemI];
- }
-
- /// Return true if the specified store with truncation is legal on this
- /// target.
- bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
- return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
- }
-
- /// Return true if the specified store with truncation has solution on this
- /// target.
- bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
- return isTypeLegal(ValVT) &&
- (getTruncStoreAction(ValVT, MemVT) == Legal ||
- getTruncStoreAction(ValVT, MemVT) == Custom);
- }
-
- /// Return how the indexed load should be treated: either it is legal, needs
- /// to be promoted to a larger size, needs to be expanded to some other code
- /// sequence, or the target has a custom expander for it.
- LegalizeAction
- getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
- assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
- "Table isn't big enough!");
- unsigned Ty = (unsigned)VT.SimpleTy;
- return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
- }
-
- /// Return true if the specified indexed load is legal on this target.
- bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
- /// Return how the indexed store should be treated: either it is legal, needs
- /// to be promoted to a larger size, needs to be expanded to some other code
- /// sequence, or the target has a custom expander for it.
- LegalizeAction
- getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
- assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
- "Table isn't big enough!");
- unsigned Ty = (unsigned)VT.SimpleTy;
- return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
- }
-
- /// Return true if the specified indexed load is legal on this target.
- bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
- /// Return how the condition code should be treated: either it is legal, needs
- /// to be expanded to some other code sequence, or the target has a custom
- /// expander for it.
- LegalizeAction
- getCondCodeAction(ISD::CondCode CC, MVT VT) const {
- assert((unsigned)CC < array_lengthof(CondCodeActions) &&
- ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
- "Table isn't big enough!");
- // See setCondCodeAction for how this is encoded.
- uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
- uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
- LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
- assert(Action != Promote && "Can't promote condition code!");
- return Action;
- }
-
- /// Return true if the specified condition code is legal on this target.
- bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
- return
- getCondCodeAction(CC, VT) == Legal ||
- getCondCodeAction(CC, VT) == Custom;
- }
-
- /// If the action for this operation is to promote, this method returns the
- /// ValueType to promote to.
- MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
- assert(getOperationAction(Op, VT) == Promote &&
- "This operation isn't promoted!");
-
- // See if this has an explicit type specified.
- std::map<std::pair<unsigned, MVT::SimpleValueType>,
- MVT::SimpleValueType>::const_iterator PTTI =
- PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
- if (PTTI != PromoteToType.end()) return PTTI->second;
-
- assert((VT.isInteger() || VT.isFloatingPoint()) &&
- "Cannot autopromote this type, add it with AddPromotedToType.");
-
- MVT NVT = VT;
- do {
- NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
- assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
- "Didn't find type to promote to!");
- } while (!isTypeLegal(NVT) ||
- getOperationAction(Op, NVT) == Promote);
- return NVT;
- }
-
- /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
- /// operations except for the pointer size. If AllowUnknown is true, this
- /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
- /// otherwise it will assert.
- EVT getValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
- // Lower scalar pointers to native pointer types.
- if (PointerType *PTy = dyn_cast<PointerType>(Ty))
- return getPointerTy(DL, PTy->getAddressSpace());
-
- if (Ty->isVectorTy()) {
- VectorType *VTy = cast<VectorType>(Ty);
- Type *Elm = VTy->getElementType();
- // Lower vectors of pointers to native pointer types.
- if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
- EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
- Elm = PointerTy.getTypeForEVT(Ty->getContext());
- }
-
- return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
- VTy->getNumElements());
- }
- return EVT::getEVT(Ty, AllowUnknown);
- }
-
- /// Return the MVT corresponding to this LLVM type. See getValueType.
- MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
- return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
- }
-
- /// Return the desired alignment for ByVal or InAlloca aggregate function
- /// arguments in the caller parameter area. This is the actual alignment, not
- /// its logarithm.
- virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
-
- /// Return the type of registers that this ValueType will eventually require.
- MVT getRegisterType(MVT VT) const {
- assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
- return RegisterTypeForVT[VT.SimpleTy];
- }
-
- /// Return the type of registers that this ValueType will eventually require.
- MVT getRegisterType(LLVMContext &Context, EVT VT) const {
- if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT().SimpleTy <
- array_lengthof(RegisterTypeForVT));
- return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
- }
- if (VT.isVector()) {
- EVT VT1;
- MVT RegisterVT;
- unsigned NumIntermediates;
- (void)getVectorTypeBreakdown(Context, VT, VT1,
- NumIntermediates, RegisterVT);
- return RegisterVT;
- }
- if (VT.isInteger()) {
- return getRegisterType(Context, getTypeToTransformTo(Context, VT));
- }
- llvm_unreachable("Unsupported extended type!");
- }
-
- /// Return the number of registers that this ValueType will eventually
- /// require.
- ///
- /// This is one for any types promoted to live in larger registers, but may be
- /// more than one for types (like i64) that are split into pieces. For types
- /// like i140, which are first promoted then expanded, it is the number of
- /// registers needed to hold all the bits of the original type. For an i140
- /// on a 32 bit machine this means 5 registers.
- unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
- if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT().SimpleTy <
- array_lengthof(NumRegistersForVT));
- return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
- }
- if (VT.isVector()) {
- EVT VT1;
- MVT VT2;
- unsigned NumIntermediates;
- return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
- }
- if (VT.isInteger()) {
- unsigned BitWidth = VT.getSizeInBits();
- unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
- return (BitWidth + RegWidth - 1) / RegWidth;
- }
- llvm_unreachable("Unsupported extended type!");
- }
-
- /// Certain combinations of ABIs, Targets and features require that types
- /// are legal for some operations and not for other operations.
- /// For MIPS all vector types must be passed through the integer register set.
- virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
- return getRegisterType(VT);
- }
-
- virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
- EVT VT) const {
- return getRegisterType(Context, VT);
- }
-
- /// Certain targets require unusual breakdowns of certain types. For MIPS,
- /// this occurs when a vector type is used, as vector are passed through the
- /// integer register set.
- virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
- EVT VT) const {
- return getNumRegisters(Context, VT);
- }
-
- /// Certain targets have context senstive alignment requirements, where one
- /// type has the alignment requirement of another type.
- virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
- DataLayout DL) const {
- return DL.getABITypeAlignment(ArgTy);
- }
-
- /// If true, then instruction selection should seek to shrink the FP constant
- /// of the specified type to a smaller type in order to save space and / or
- /// reduce runtime.
- virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
-
- // Return true if it is profitable to reduce the given load node to a smaller
- // type.
- //
- // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
- virtual bool shouldReduceLoadWidth(SDNode *Load,
- ISD::LoadExtType ExtTy,
- EVT NewVT) const {
- return true;
- }
-
- /// When splitting a value of the specified type into parts, does the Lo
- /// or Hi part come first? This usually follows the endianness, except
- /// for ppcf128, where the Hi part always comes first.
- bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
- return DL.isBigEndian() || VT == MVT::ppcf128;
- }
-
- /// If true, the target has custom DAG combine transformations that it can
- /// perform for the specified node.
- bool hasTargetDAGCombine(ISD::NodeType NT) const {
- assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
- return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
- }
-
- unsigned getGatherAllAliasesMaxDepth() const {
- return GatherAllAliasesMaxDepth;
- }
-
- /// Returns the size of the platform's va_list object.
- virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
- return getPointerTy(DL).getSizeInBits();
- }
-
- /// \brief Get maximum # of store operations permitted for llvm.memset
- ///
- /// This function returns the maximum number of store operations permitted
- /// to replace a call to llvm.memset. The value is set by the target at the
- /// performance threshold for such a replacement. If OptSize is true,
- /// return the limit for functions that have OptSize attribute.
- unsigned getMaxStoresPerMemset(bool OptSize) const {
- return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
- }
-
- /// \brief Get maximum # of store operations permitted for llvm.memcpy
- ///
- /// This function returns the maximum number of store operations permitted
- /// to replace a call to llvm.memcpy. The value is set by the target at the
- /// performance threshold for such a replacement. If OptSize is true,
- /// return the limit for functions that have OptSize attribute.
- unsigned getMaxStoresPerMemcpy(bool OptSize) const {
- return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
- }
-
- /// Get maximum # of load operations permitted for memcmp
- ///
- /// This function returns the maximum number of load operations permitted
- /// to replace a call to memcmp. The value is set by the target at the
- /// performance threshold for such a replacement. If OptSize is true,
- /// return the limit for functions that have OptSize attribute.
- unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
- return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
- }
-
- /// \brief Get maximum # of store operations permitted for llvm.memmove
- ///
- /// This function returns the maximum number of store operations permitted
- /// to replace a call to llvm.memmove. The value is set by the target at the
- /// performance threshold for such a replacement. If OptSize is true,
- /// return the limit for functions that have OptSize attribute.
- unsigned getMaxStoresPerMemmove(bool OptSize) const {
- return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
- }
-
- /// \brief Determine if the target supports unaligned memory accesses.
- ///
- /// This function returns true if the target allows unaligned memory accesses
- /// of the specified type in the given address space. If true, it also returns
- /// whether the unaligned memory access is "fast" in the last argument by
- /// reference. This is used, for example, in situations where an array
- /// copy/move/set is converted to a sequence of store operations. Its use
- /// helps to ensure that such replacements don't generate code that causes an
- /// alignment error (trap) on the target machine.
- virtual bool allowsMisalignedMemoryAccesses(EVT,
- unsigned AddrSpace = 0,
- unsigned Align = 1,
- bool * /*Fast*/ = nullptr) const {
- return false;
- }
-
- /// Return true if the target supports a memory access of this type for the
- /// given address space and alignment. If the access is allowed, the optional
- /// final parameter returns if the access is also fast (as defined by the
- /// target).
- bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
- unsigned AddrSpace = 0, unsigned Alignment = 1,
- bool *Fast = nullptr) const;
-
- /// Returns the target specific optimal type for load and store operations as
- /// a result of memset, memcpy, and memmove lowering.
- ///
- /// If DstAlign is zero that means it's safe to destination alignment can
- /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
- /// a need to check it against alignment requirement, probably because the
- /// source does not need to be loaded. If 'IsMemset' is true, that means it's
- /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
- /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
- /// does not need to be loaded. It returns EVT::Other if the type should be
- /// determined using generic target-independent logic.
- virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
- unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
- bool /*IsMemset*/,
- bool /*ZeroMemset*/,
- bool /*MemcpyStrSrc*/,
- MachineFunction &/*MF*/) const {
- return MVT::Other;
- }
-
- /// Returns true if it's safe to use load / store of the specified type to
- /// expand memcpy / memset inline.
- ///
- /// This is mostly true for all types except for some special cases. For
- /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
- /// fstpl which also does type conversion. Note the specified type doesn't
- /// have to be legal as the hook is used before type legalization.
- virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
-
- /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
- bool usesUnderscoreSetJmp() const {
- return UseUnderscoreSetJmp;
- }
-
- /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
- bool usesUnderscoreLongJmp() const {
- return UseUnderscoreLongJmp;
- }
-
- /// Return lower limit for number of blocks in a jump table.
- unsigned getMinimumJumpTableEntries() const;
-
- /// Return lower limit of the density in a jump table.
- unsigned getMinimumJumpTableDensity(bool OptForSize) const;
-
- /// Return upper limit for number of entries in a jump table.
- /// Zero if no limit.
- unsigned getMaximumJumpTableSize() const;
-
- virtual bool isJumpTableRelative() const {
- return TM.isPositionIndependent();
- }
-
- /// If a physical register, this specifies the register that
- /// llvm.savestack/llvm.restorestack should save and restore.
- unsigned getStackPointerRegisterToSaveRestore() const {
- return StackPointerRegisterToSaveRestore;
- }
-
- /// If a physical register, this returns the register that receives the
- /// exception address on entry to an EH pad.
- virtual unsigned
- getExceptionPointerRegister(const Constant *PersonalityFn) const {
- // 0 is guaranteed to be the NoRegister value on all targets
- return 0;
- }
-
- /// If a physical register, this returns the register that receives the
- /// exception typeid on entry to a landing pad.
- virtual unsigned
- getExceptionSelectorRegister(const Constant *PersonalityFn) const {
- // 0 is guaranteed to be the NoRegister value on all targets
- return 0;
- }
-
- virtual bool needsFixedCatchObjects() const {
- report_fatal_error("Funclet EH is not implemented for this target");
- }
-
- /// Returns the target's jmp_buf size in bytes (if never set, the default is
- /// 200)
- unsigned getJumpBufSize() const {
- return JumpBufSize;
- }
-
- /// Returns the target's jmp_buf alignment in bytes (if never set, the default
- /// is 0)
- unsigned getJumpBufAlignment() const {
- return JumpBufAlignment;
- }
-
- /// Return the minimum stack alignment of an argument.
- unsigned getMinStackArgumentAlignment() const {
- return MinStackArgumentAlignment;
- }
-
- /// Return the minimum function alignment.
- unsigned getMinFunctionAlignment() const {
- return MinFunctionAlignment;
- }
-
- /// Return the preferred function alignment.
- unsigned getPrefFunctionAlignment() const {
- return PrefFunctionAlignment;
- }
-
- /// Return the preferred loop alignment.
- virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
- return PrefLoopAlignment;
- }
-
- /// If the target has a standard location for the stack protector guard,
- /// returns the address of that location. Otherwise, returns nullptr.
- /// DEPRECATED: please override useLoadStackGuardNode and customize
- /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
- virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
-
- /// Inserts necessary declarations for SSP (stack protection) purpose.
- /// Should be used only when getIRStackGuard returns nullptr.
- virtual void insertSSPDeclarations(Module &M) const;
-
- /// Return the variable that's previously inserted by insertSSPDeclarations,
- /// if any, otherwise return nullptr. Should be used only when
- /// getIRStackGuard returns nullptr.
- virtual Value *getSDagStackGuard(const Module &M) const;
-
- /// If the target has a standard stack protection check function that
- /// performs validation and error handling, returns the function. Otherwise,
- /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
- /// Should be used only when getIRStackGuard returns nullptr.
- virtual Value *getSSPStackGuardCheck(const Module &M) const;
-
-protected:
- Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
- bool UseTLS) const;
-
-public:
- /// Returns the target-specific address of the unsafe stack pointer.
- virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
-
- /// Returns the name of the symbol used to emit stack probes or the empty
- /// string if not applicable.
- virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
- return "";
- }
-
- /// Returns true if a cast between SrcAS and DestAS is a noop.
- virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
- return false;
- }
-
- /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
- /// are happy to sink it into basic blocks.
- virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
- return isNoopAddrSpaceCast(SrcAS, DestAS);
- }
-
- /// Return true if the pointer arguments to CI should be aligned by aligning
- /// the object whose address is being passed. If so then MinSize is set to the
- /// minimum size the object must be to be aligned and PrefAlign is set to the
- /// preferred alignment.
- virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
- unsigned & /*PrefAlign*/) const {
- return false;
- }
-
- //===--------------------------------------------------------------------===//
- /// \name Helpers for TargetTransformInfo implementations
- /// @{
-
- /// Get the ISD node that corresponds to the Instruction class opcode.
- int InstructionOpcodeToISD(unsigned Opcode) const;
-
- /// Estimate the cost of type-legalization and the legalized type.
- std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
- Type *Ty) const;
-
- /// @}
-
- //===--------------------------------------------------------------------===//
- /// \name Helpers for atomic expansion.
- /// @{
-
- /// Returns the maximum atomic operation size (in bits) supported by
- /// the backend. Atomic operations greater than this size (as well
- /// as ones that are not naturally aligned), will be expanded by
- /// AtomicExpandPass into an __atomic_* library call.
- unsigned getMaxAtomicSizeInBitsSupported() const {
- return MaxAtomicSizeInBitsSupported;
- }
-
- /// Returns the size of the smallest cmpxchg or ll/sc instruction
- /// the backend supports. Any smaller operations are widened in
- /// AtomicExpandPass.
- ///
- /// Note that *unlike* operations above the maximum size, atomic ops
- /// are still natively supported below the minimum; they just
- /// require a more complex expansion.
- unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
-
- /// Whether AtomicExpandPass should automatically insert fences and reduce
- /// ordering for this atomic. This should be true for most architectures with
- /// weak memory ordering. Defaults to false.
- virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
- return false;
- }
-
- /// Perform a load-linked operation on Addr, returning a "Value *" with the
- /// corresponding pointee type. This may entail some non-trivial operations to
- /// truncate or reconstruct types that will be illegal in the backend. See
- /// ARMISelLowering for an example implementation.
- virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
- AtomicOrdering Ord) const {
- llvm_unreachable("Load linked unimplemented on this target");
- }
-
- /// Perform a store-conditional operation to Addr. Return the status of the
- /// store. This should be 0 if the store succeeded, non-zero otherwise.
- virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
- Value *Addr, AtomicOrdering Ord) const {
- llvm_unreachable("Store conditional unimplemented on this target");
- }
-
- /// Inserts in the IR a target-specific intrinsic specifying a fence.
- /// It is called by AtomicExpandPass before expanding an
- /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
- /// if shouldInsertFencesForAtomic returns true.
- ///
- /// Inst is the original atomic instruction, prior to other expansions that
- /// may be performed.
- ///
- /// This function should either return a nullptr, or a pointer to an IR-level
- /// Instruction*. Even complex fence sequences can be represented by a
- /// single Instruction* through an intrinsic to be lowered later.
- /// Backends should override this method to produce target-specific intrinsic
- /// for their fences.
- /// FIXME: Please note that the default implementation here in terms of
- /// IR-level fences exists for historical/compatibility reasons and is
- /// *unsound* ! Fences cannot, in general, be used to restore sequential
- /// consistency. For example, consider the following example:
- /// atomic<int> x = y = 0;
- /// int r1, r2, r3, r4;
- /// Thread 0:
- /// x.store(1);
- /// Thread 1:
- /// y.store(1);
- /// Thread 2:
- /// r1 = x.load();
- /// r2 = y.load();
- /// Thread 3:
- /// r3 = y.load();
- /// r4 = x.load();
- /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
- /// seq_cst. But if they are lowered to monotonic accesses, no amount of
- /// IR-level fences can prevent it.
- /// @{
- virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
- AtomicOrdering Ord) const {
- if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
- return Builder.CreateFence(Ord);
- else
- return nullptr;
- }
-
- virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
- Instruction *Inst,
- AtomicOrdering Ord) const {
- if (isAcquireOrStronger(Ord))
- return Builder.CreateFence(Ord);
- else
- return nullptr;
- }
- /// @}
-
- // Emits code that executes when the comparison result in the ll/sc
- // expansion of a cmpxchg instruction is such that the store-conditional will
- // not execute. This makes it possible to balance out the load-linked with
- // a dedicated instruction, if desired.
- // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
- // be unnecessarily held, except if clrex, inserted by this hook, is executed.
- virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
-
- /// Returns true if the given (atomic) store should be expanded by the
- /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
- virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
- return false;
- }
-
- /// Returns true if arguments should be sign-extended in lib calls.
- virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
- return IsSigned;
- }
-
- /// Returns how the given (atomic) load should be expanded by the
- /// IR-level AtomicExpand pass.
- virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
- return AtomicExpansionKind::None;
- }
-
- /// Returns true if the given atomic cmpxchg should be expanded by the
- /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
- /// (through emitLoadLinked() and emitStoreConditional()).
- virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
- return false;
- }
-
- /// Returns how the IR-level AtomicExpand pass should expand the given
- /// AtomicRMW, if at all. Default is to never expand.
- virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
- return AtomicExpansionKind::None;
- }
-
- /// On some platforms, an AtomicRMW that never actually modifies the value
- /// (such as fetch_add of 0) can be turned into a fence followed by an
- /// atomic load. This may sound useless, but it makes it possible for the
- /// processor to keep the cacheline shared, dramatically improving
- /// performance. And such idempotent RMWs are useful for implementing some
- /// kinds of locks, see for example (justification + benchmarks):
- /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
- /// This method tries doing that transformation, returning the atomic load if
- /// it succeeds, and nullptr otherwise.
- /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
- /// another round of expansion.
- virtual LoadInst *
- lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
- return nullptr;
- }
-
- /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
- /// SIGN_EXTEND, or ANY_EXTEND).
- virtual ISD::NodeType getExtendForAtomicOps() const {
- return ISD::ZERO_EXTEND;
- }
-
- /// @}
-
- /// Returns true if we should normalize
- /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
- /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
- /// that it saves us from materializing N0 and N1 in an integer register.
- /// Targets that are able to perform and/or on flags should return false here.
- virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
- EVT VT) const {
- // If a target has multiple condition registers, then it likely has logical
- // operations on those registers.
- if (hasMultipleConditionRegisters())
- return false;
- // Only do the transform if the value won't be split into multiple
- // registers.
- LegalizeTypeAction Action = getTypeAction(Context, VT);
- return Action != TypeExpandInteger && Action != TypeExpandFloat &&
- Action != TypeSplitVector;
- }
-
- /// Return true if a select of constants (select Cond, C1, C2) should be
- /// transformed into simple math ops with the condition value. For example:
- /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
- virtual bool convertSelectOfConstantsToMath(EVT VT) const {
- return false;
- }
-
- //===--------------------------------------------------------------------===//
- // TargetLowering Configuration Methods - These methods should be invoked by
- // the derived class constructor to configure this object for the target.
- //
-protected:
- /// Specify how the target extends the result of integer and floating point
- /// boolean values from i1 to a wider type. See getBooleanContents.
- void setBooleanContents(BooleanContent Ty) {
- BooleanContents = Ty;
- BooleanFloatContents = Ty;
- }
-
- /// Specify how the target extends the result of integer and floating point
- /// boolean values from i1 to a wider type. See getBooleanContents.
- void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
- BooleanContents = IntTy;
- BooleanFloatContents = FloatTy;
- }
-
- /// Specify how the target extends the result of a vector boolean value from a
- /// vector of i1 to a wider type. See getBooleanContents.
- void setBooleanVectorContents(BooleanContent Ty) {
- BooleanVectorContents = Ty;
- }
-
- /// Specify the target scheduling preference.
- void setSchedulingPreference(Sched::Preference Pref) {
- SchedPreferenceInfo = Pref;
- }
-
- /// Indicate whether this target prefers to use _setjmp to implement
- /// llvm.setjmp or the version without _. Defaults to false.
- void setUseUnderscoreSetJmp(bool Val) {
- UseUnderscoreSetJmp = Val;
- }
-
- /// Indicate whether this target prefers to use _longjmp to implement
- /// llvm.longjmp or the version without _. Defaults to false.
- void setUseUnderscoreLongJmp(bool Val) {
- UseUnderscoreLongJmp = Val;
- }
-
- /// Indicate the minimum number of blocks to generate jump tables.
- void setMinimumJumpTableEntries(unsigned Val);
-
- /// Indicate the maximum number of entries in jump tables.
- /// Set to zero to generate unlimited jump tables.
- void setMaximumJumpTableSize(unsigned);
-
- /// If set to a physical register, this specifies the register that
- /// llvm.savestack/llvm.restorestack should save and restore.
- void setStackPointerRegisterToSaveRestore(unsigned R) {
- StackPointerRegisterToSaveRestore = R;
- }
-
- /// Tells the code generator that the target has multiple (allocatable)
- /// condition registers that can be used to store the results of comparisons
- /// for use by selects and conditional branches. With multiple condition
- /// registers, the code generator will not aggressively sink comparisons into
- /// the blocks of their users.
- void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
- HasMultipleConditionRegisters = hasManyRegs;
- }
-
- /// Tells the code generator that the target has BitExtract instructions.
- /// The code generator will aggressively sink "shift"s into the blocks of
- /// their users if the users will generate "and" instructions which can be
- /// combined with "shift" to BitExtract instructions.
- void setHasExtractBitsInsn(bool hasExtractInsn = true) {
- HasExtractBitsInsn = hasExtractInsn;
- }
-
- /// Tells the code generator not to expand logic operations on comparison
- /// predicates into separate sequences that increase the amount of flow
- /// control.
- void setJumpIsExpensive(bool isExpensive = true);
-
- /// Tells the code generator that this target supports floating point
- /// exceptions and cares about preserving floating point exception behavior.
- void setHasFloatingPointExceptions(bool FPExceptions = true) {
- HasFloatingPointExceptions = FPExceptions;
- }
-
- /// Tells the code generator which bitwidths to bypass.
- void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
- BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
- }
-
- /// Add the specified register class as an available regclass for the
- /// specified value type. This indicates the selector can handle values of
- /// that class natively.
- void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
- assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
- RegClassForVT[VT.SimpleTy] = RC;
- }
-
- /// Return the largest legal super-reg register class of the register class
- /// for the specified type and its associated "cost".
- virtual std::pair<const TargetRegisterClass *, uint8_t>
- findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
-
- /// Once all of the register classes are added, this allows us to compute
- /// derived properties we expose.
- void computeRegisterProperties(const TargetRegisterInfo *TRI);
-
- /// Indicate that the specified operation does not work with the specified
- /// type and indicate what to do about it. Note that VT may refer to either
- /// the type of a result or that of an operand of Op.
- void setOperationAction(unsigned Op, MVT VT,
- LegalizeAction Action) {
- assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
- OpActions[(unsigned)VT.SimpleTy][Op] = Action;
- }
-
- /// Indicate that the specified load with extension does not work with the
- /// specified type and indicate what to do about it.
- void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
- LegalizeAction Action) {
- assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
- MemVT.isValid() && "Table isn't big enough!");
- assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
- unsigned Shift = 4 * ExtType;
- LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
- LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
- }
-
- /// Indicate that the specified truncating store does not work with the
- /// specified type and indicate what to do about it.
- void setTruncStoreAction(MVT ValVT, MVT MemVT,
- LegalizeAction Action) {
- assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
- TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
- }
-
- /// Indicate that the specified indexed load does or does not work with the
- /// specified type and indicate what to do abort it.
- ///
- /// NOTE: All indexed mode loads are initialized to Expand in
- /// TargetLowering.cpp
- void setIndexedLoadAction(unsigned IdxMode, MVT VT,
- LegalizeAction Action) {
- assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
- (unsigned)Action < 0xf && "Table isn't big enough!");
- // Load action are kept in the upper half.
- IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
- IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
- }
-
- /// Indicate that the specified indexed store does or does not work with the
- /// specified type and indicate what to do about it.
- ///
- /// NOTE: All indexed mode stores are initialized to Expand in
- /// TargetLowering.cpp
- void setIndexedStoreAction(unsigned IdxMode, MVT VT,
- LegalizeAction Action) {
- assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
- (unsigned)Action < 0xf && "Table isn't big enough!");
- // Store action are kept in the lower half.
- IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
- IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
- }
-
- /// Indicate that the specified condition code is or isn't supported on the
- /// target and indicate what to do about it.
- void setCondCodeAction(ISD::CondCode CC, MVT VT,
- LegalizeAction Action) {
- assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
- "Table isn't big enough!");
- assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
- /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
- /// value and the upper 29 bits index into the second dimension of the array
- /// to select what 32-bit value to use.
- uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
- CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
- CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
- }
-
- /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
- /// to trying a larger integer/fp until it can find one that works. If that
- /// default is insufficient, this method can be used by the target to override
- /// the default.
- void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
- PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
- }
-
- /// Convenience method to set an operation to Promote and specify the type
- /// in a single call.
- void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
- setOperationAction(Opc, OrigVT, Promote);
- AddPromotedToType(Opc, OrigVT, DestVT);
- }
-
- /// Targets should invoke this method for each target independent node that
- /// they want to provide a custom DAG combiner for by implementing the
- /// PerformDAGCombine virtual method.
- void setTargetDAGCombine(ISD::NodeType NT) {
- assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
- TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
- }
-
- /// Set the target's required jmp_buf buffer size (in bytes); default is 200
- void setJumpBufSize(unsigned Size) {
- JumpBufSize = Size;
- }
-
- /// Set the target's required jmp_buf buffer alignment (in bytes); default is
- /// 0
- void setJumpBufAlignment(unsigned Align) {
- JumpBufAlignment = Align;
- }
-
- /// Set the target's minimum function alignment (in log2(bytes))
- void setMinFunctionAlignment(unsigned Align) {
- MinFunctionAlignment = Align;
- }
-
- /// Set the target's preferred function alignment. This should be set if
- /// there is a performance benefit to higher-than-minimum alignment (in
- /// log2(bytes))
- void setPrefFunctionAlignment(unsigned Align) {
- PrefFunctionAlignment = Align;
- }
-
- /// Set the target's preferred loop alignment. Default alignment is zero, it
- /// means the target does not care about loop alignment. The alignment is
- /// specified in log2(bytes). The target may also override
- /// getPrefLoopAlignment to provide per-loop values.
- void setPrefLoopAlignment(unsigned Align) {
- PrefLoopAlignment = Align;
- }
-
- /// Set the minimum stack alignment of an argument (in log2(bytes)).
- void setMinStackArgumentAlignment(unsigned Align) {
- MinStackArgumentAlignment = Align;
- }
-
- /// Set the maximum atomic operation size supported by the
- /// backend. Atomic operations greater than this size (as well as
- /// ones that are not naturally aligned), will be expanded by
- /// AtomicExpandPass into an __atomic_* library call.
- void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
- MaxAtomicSizeInBitsSupported = SizeInBits;
- }
-
- // Sets the minimum cmpxchg or ll/sc size supported by the backend.
- void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
- MinCmpXchgSizeInBits = SizeInBits;
- }
-
-public:
- //===--------------------------------------------------------------------===//
- // Addressing mode description hooks (used by LSR etc).
- //
-
- /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
- /// instructions reading the address. This allows as much computation as
- /// possible to be done in the address mode for that operand. This hook lets
- /// targets also pass back when this should be done on intrinsics which
- /// load/store.
- virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
- SmallVectorImpl<Value*> &/*Ops*/,
- Type *&/*AccessTy*/) const {
- return false;
- }
-
- /// This represents an addressing mode of:
- /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
- /// If BaseGV is null, there is no BaseGV.
- /// If BaseOffs is zero, there is no base offset.
- /// If HasBaseReg is false, there is no base register.
- /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
- /// no scale.
- struct AddrMode {
- GlobalValue *BaseGV = nullptr;
- int64_t BaseOffs = 0;
- bool HasBaseReg = false;
- int64_t Scale = 0;
- AddrMode() = default;
- };
-
- /// Return true if the addressing mode represented by AM is legal for this
- /// target, for a load/store of the specified type.
- ///
- /// The type may be VoidTy, in which case only return true if the addressing
- /// mode is legal for a load/store of any legal type. TODO: Handle
- /// pre/postinc as well.
- ///
- /// If the address space cannot be determined, it will be -1.
- ///
- /// TODO: Remove default argument
- virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
- Type *Ty, unsigned AddrSpace,
- Instruction *I = nullptr) const;
-
- /// \brief Return the cost of the scaling factor used in the addressing mode
- /// represented by AM for this target, for a load/store of the specified type.
- ///
- /// If the AM is supported, the return value must be >= 0.
- /// If the AM is not supported, it returns a negative value.
- /// TODO: Handle pre/postinc as well.
- /// TODO: Remove default argument
- virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
- Type *Ty, unsigned AS = 0) const {
- // Default: assume that any scaling factor used in a legal AM is free.
- if (isLegalAddressingMode(DL, AM, Ty, AS))
- return 0;
- return -1;
- }
-
- /// Return true if the specified immediate is legal icmp immediate, that is
- /// the target has icmp instructions which can compare a register against the
- /// immediate without having to materialize the immediate into a register.
- virtual bool isLegalICmpImmediate(int64_t) const {
- return true;
- }
-
- /// Return true if the specified immediate is legal add immediate, that is the
- /// target has add instructions which can add a register with the immediate
- /// without having to materialize the immediate into a register.
- virtual bool isLegalAddImmediate(int64_t) const {
- return true;
- }
-
- /// Return true if it's significantly cheaper to shift a vector by a uniform
- /// scalar than by an amount which will vary across each lane. On x86, for
- /// example, there is a "psllw" instruction for the former case, but no simple
- /// instruction for a general "a << b" operation on vectors.
- virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
- return false;
- }
-
- /// Returns true if the opcode is a commutative binary operation.
- virtual bool isCommutativeBinOp(unsigned Opcode) const {
- // FIXME: This should get its info from the td file.
- switch (Opcode) {
- case ISD::ADD:
- case ISD::SMIN:
- case ISD::SMAX:
- case ISD::UMIN:
- case ISD::UMAX:
- case ISD::MUL:
- case ISD::MULHU:
- case ISD::MULHS:
- case ISD::SMUL_LOHI:
- case ISD::UMUL_LOHI:
- case ISD::FADD:
- case ISD::FMUL:
- case ISD::AND:
- case ISD::OR:
- case ISD::XOR:
- case ISD::SADDO:
- case ISD::UADDO:
- case ISD::ADDC:
- case ISD::ADDE:
- case ISD::FMINNUM:
- case ISD::FMAXNUM:
- case ISD::FMINNAN:
- case ISD::FMAXNAN:
- return true;
- default: return false;
- }
- }
-
- /// Return true if it's free to truncate a value of type FromTy to type
- /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
- /// by referencing its sub-register AX.
- /// Targets must return false when FromTy <= ToTy.
- virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
- return false;
- }
-
- /// Return true if a truncation from FromTy to ToTy is permitted when deciding
- /// whether a call is in tail position. Typically this means that both results
- /// would be assigned to the same register or stack slot, but it could mean
- /// the target performs adequate checks of its own before proceeding with the
- /// tail call. Targets must return false when FromTy <= ToTy.
- virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
- return false;
- }
-
- virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
- return false;
- }
-
- virtual bool isProfitableToHoist(Instruction *I) const { return true; }
-
- /// Return true if the extension represented by \p I is free.
- /// Unlikely the is[Z|FP]ExtFree family which is based on types,
- /// this method can use the context provided by \p I to decide
- /// whether or not \p I is free.
- /// This method extends the behavior of the is[Z|FP]ExtFree family.
- /// In other words, if is[Z|FP]Free returns true, then this method
- /// returns true as well. The converse is not true.
- /// The target can perform the adequate checks by overriding isExtFreeImpl.
- /// \pre \p I must be a sign, zero, or fp extension.
- bool isExtFree(const Instruction *I) const {
- switch (I->getOpcode()) {
- case Instruction::FPExt:
- if (isFPExtFree(EVT::getEVT(I->getType()),
- EVT::getEVT(I->getOperand(0)->getType())))
- return true;
- break;
- case Instruction::ZExt:
- if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
- return true;
- break;
- case Instruction::SExt:
- break;
- default:
- llvm_unreachable("Instruction is not an extension");
- }
- return isExtFreeImpl(I);
- }
-
- /// Return true if \p Load and \p Ext can form an ExtLoad.
- /// For example, in AArch64
- /// %L = load i8, i8* %ptr
- /// %E = zext i8 %L to i32
- /// can be lowered into one load instruction
- /// ldrb w0, [x0]
- bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
- const DataLayout &DL) const {
- EVT VT = getValueType(DL, Ext->getType());
- EVT LoadVT = getValueType(DL, Load->getType());
-
- // If the load has other users and the truncate is not free, the ext
- // probably isn't free.
- if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
- !isTruncateFree(Ext->getType(), Load->getType()))
- return false;
-
- // Check whether the target supports casts folded into loads.
- unsigned LType;
- if (isa<ZExtInst>(Ext))
- LType = ISD::ZEXTLOAD;
- else {
- assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
- LType = ISD::SEXTLOAD;
- }
-
- return isLoadExtLegal(LType, VT, LoadVT);
- }
-
- /// Return true if any actual instruction that defines a value of type FromTy
- /// implicitly zero-extends the value to ToTy in the result register.
- ///
- /// The function should return true when it is likely that the truncate can
- /// be freely folded with an instruction defining a value of FromTy. If
- /// the defining instruction is unknown (because you're looking at a
- /// function argument, PHI, etc.) then the target may require an
- /// explicit truncate, which is not necessarily free, but this function
- /// does not deal with those cases.
- /// Targets must return false when FromTy >= ToTy.
- virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
- return false;
- }
-
- virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
- return false;
- }
-
- /// Return true if the target supplies and combines to a paired load
- /// two loaded values of type LoadedType next to each other in memory.
- /// RequiredAlignment gives the minimal alignment constraints that must be met
- /// to be able to select this paired load.
- ///
- /// This information is *not* used to generate actual paired loads, but it is
- /// used to generate a sequence of loads that is easier to combine into a
- /// paired load.
- /// For instance, something like this:
- /// a = load i64* addr
- /// b = trunc i64 a to i32
- /// c = lshr i64 a, 32
- /// d = trunc i64 c to i32
- /// will be optimized into:
- /// b = load i32* addr1
- /// d = load i32* addr2
- /// Where addr1 = addr2 +/- sizeof(i32).
- ///
- /// In other words, unless the target performs a post-isel load combining,
- /// this information should not be provided because it will generate more
- /// loads.
- virtual bool hasPairedLoad(EVT /*LoadedType*/,
- unsigned & /*RequiredAlignment*/) const {
- return false;
- }
-
- /// \brief Get the maximum supported factor for interleaved memory accesses.
- /// Default to be the minimum interleave factor: 2.
- virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
-
- /// \brief Lower an interleaved load to target specific intrinsics. Return
- /// true on success.
- ///
- /// \p LI is the vector load instruction.
- /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
- /// \p Indices is the corresponding indices for each shufflevector.
- /// \p Factor is the interleave factor.
- virtual bool lowerInterleavedLoad(LoadInst *LI,
- ArrayRef<ShuffleVectorInst *> Shuffles,
- ArrayRef<unsigned> Indices,
- unsigned Factor) const {
- return false;
- }
-
- /// \brief Lower an interleaved store to target specific intrinsics. Return
- /// true on success.
- ///
- /// \p SI is the vector store instruction.
- /// \p SVI is the shufflevector to RE-interleave the stored vector.
- /// \p Factor is the interleave factor.
- virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
- unsigned Factor) const {
- return false;
- }
-
- /// Return true if zero-extending the specific node Val to type VT2 is free
- /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
- /// because it's folded such as X86 zero-extending loads).
- virtual bool isZExtFree(SDValue Val, EVT VT2) const {
- return isZExtFree(Val.getValueType(), VT2);
- }
-
- /// Return true if an fpext operation is free (for instance, because
- /// single-precision floating-point numbers are implicitly extended to
- /// double-precision).
- virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
- assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
- "invalid fpext types");
- return false;
- }
-
- /// Return true if an fpext operation input to an \p Opcode operation is free
- /// (for instance, because half-precision floating-point numbers are
- /// implicitly extended to float-precision) for an FMA instruction.
- virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
- assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
- "invalid fpext types");
- return isFPExtFree(DestVT, SrcVT);
- }
-
- /// Return true if folding a vector load into ExtVal (a sign, zero, or any
- /// extend node) is profitable.
- virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
-
- /// Return true if an fneg operation is free to the point where it is never
- /// worthwhile to replace it with a bitwise operation.
- virtual bool isFNegFree(EVT VT) const {
- assert(VT.isFloatingPoint());
- return false;
- }
-
- /// Return true if an fabs operation is free to the point where it is never
- /// worthwhile to replace it with a bitwise operation.
- virtual bool isFAbsFree(EVT VT) const {
- assert(VT.isFloatingPoint());
- return false;
- }
-
- /// Return true if an FMA operation is faster than a pair of fmul and fadd
- /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
- /// returns true, otherwise fmuladd is expanded to fmul + fadd.
- ///
- /// NOTE: This may be called before legalization on types for which FMAs are
- /// not legal, but should return true if those types will eventually legalize
- /// to types that support FMAs. After legalization, it will only be called on
- /// types that support FMAs (via Legal or Custom actions)
- virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
- return false;
- }
-
- /// Return true if it's profitable to narrow operations of type VT1 to
- /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
- /// i32 to i16.
- virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
- return false;
- }
-
- /// \brief Return true if it is beneficial to convert a load of a constant to
- /// just the constant itself.
- /// On some targets it might be more efficient to use a combination of
- /// arithmetic instructions to materialize the constant instead of loading it
- /// from a constant pool.
- virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
- Type *Ty) const {
- return false;
- }
-
- /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
- /// from this source type with this index. This is needed because
- /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
- /// the first element, and only the target knows which lowering is cheap.
- virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
- return false;
- }
-
- // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
- // even if the vector itself has multiple uses.
- virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
- return false;
- }
-
- //===--------------------------------------------------------------------===//
- // Runtime Library hooks
- //
-
- /// Rename the default libcall routine name for the specified libcall.
- void setLibcallName(RTLIB::Libcall Call, const char *Name) {
- LibcallRoutineNames[Call] = Name;
- }
-
- /// Get the libcall routine name for the specified libcall.
- const char *getLibcallName(RTLIB::Libcall Call) const {
- return LibcallRoutineNames[Call];
- }
-
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
- CmpLibcallCCs[Call] = CC;
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
- return CmpLibcallCCs[Call];
- }
-
- /// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
- LibcallCallingConvs[Call] = CC;
- }
-
- /// Get the CallingConv that should be used for the specified libcall.
- CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
- return LibcallCallingConvs[Call];
- }
-
- /// Execute target specific actions to finalize target lowering.
- /// This is used to set extra flags in MachineFrameInformation and freezing
- /// the set of reserved registers.
- /// The default implementation just freezes the set of reserved registers.
- virtual void finalizeLowering(MachineFunction &MF) const;
-
-private:
- const TargetMachine &TM;
-
- /// Tells the code generator that the target has multiple (allocatable)
- /// condition registers that can be used to store the results of comparisons
- /// for use by selects and conditional branches. With multiple condition
- /// registers, the code generator will not aggressively sink comparisons into
- /// the blocks of their users.
- bool HasMultipleConditionRegisters;
-
- /// Tells the code generator that the target has BitExtract instructions.
- /// The code generator will aggressively sink "shift"s into the blocks of
- /// their users if the users will generate "and" instructions which can be
- /// combined with "shift" to BitExtract instructions.
- bool HasExtractBitsInsn;
-
- /// Tells the code generator to bypass slow divide or remainder
- /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
- /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
- /// div/rem when the operands are positive and less than 256.
- DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
-
- /// Tells the code generator that it shouldn't generate extra flow control
- /// instructions and should attempt to combine flow control instructions via
- /// predication.
- bool JumpIsExpensive;
-
- /// Whether the target supports or cares about preserving floating point
- /// exception behavior.
- bool HasFloatingPointExceptions;
-
- /// This target prefers to use _setjmp to implement llvm.setjmp.
- ///
- /// Defaults to false.
- bool UseUnderscoreSetJmp;
-
- /// This target prefers to use _longjmp to implement llvm.longjmp.
- ///
- /// Defaults to false.
- bool UseUnderscoreLongJmp;
-
- /// Information about the contents of the high-bits in boolean values held in
- /// a type wider than i1. See getBooleanContents.
- BooleanContent BooleanContents;
-
- /// Information about the contents of the high-bits in boolean values held in
- /// a type wider than i1. See getBooleanContents.
- BooleanContent BooleanFloatContents;
-
- /// Information about the contents of the high-bits in boolean vector values
- /// when the element type is wider than i1. See getBooleanContents.
- BooleanContent BooleanVectorContents;
-
- /// The target scheduling preference: shortest possible total cycles or lowest
- /// register usage.
- Sched::Preference SchedPreferenceInfo;
-
- /// The size, in bytes, of the target's jmp_buf buffers
- unsigned JumpBufSize;
-
- /// The alignment, in bytes, of the target's jmp_buf buffers
- unsigned JumpBufAlignment;
-
- /// The minimum alignment that any argument on the stack needs to have.
- unsigned MinStackArgumentAlignment;
-
- /// The minimum function alignment (used when optimizing for size, and to
- /// prevent explicitly provided alignment from leading to incorrect code).
- unsigned MinFunctionAlignment;
-
- /// The preferred function alignment (used when alignment unspecified and
- /// optimizing for speed).
- unsigned PrefFunctionAlignment;
-
- /// The preferred loop alignment.
- unsigned PrefLoopAlignment;
-
- /// Size in bits of the maximum atomics size the backend supports.
- /// Accesses larger than this will be expanded by AtomicExpandPass.
- unsigned MaxAtomicSizeInBitsSupported;
-
- /// Size in bits of the minimum cmpxchg or ll/sc operation the
- /// backend supports.
- unsigned MinCmpXchgSizeInBits;
-
- /// If set to a physical register, this specifies the register that
- /// llvm.savestack/llvm.restorestack should save and restore.
- unsigned StackPointerRegisterToSaveRestore;
-
- /// This indicates the default register class to use for each ValueType the
- /// target supports natively.
- const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
- unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
- MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
-
- /// This indicates the "representative" register class to use for each
- /// ValueType the target supports natively. This information is used by the
- /// scheduler to track register pressure. By default, the representative
- /// register class is the largest legal super-reg register class of the
- /// register class of the specified type. e.g. On x86, i8, i16, and i32's
- /// representative class would be GR32.
- const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
-
- /// This indicates the "cost" of the "representative" register class for each
- /// ValueType. The cost is used by the scheduler to approximate register
- /// pressure.
- uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
-
- /// For any value types we are promoting or expanding, this contains the value
- /// type that we are changing to. For Expanded types, this contains one step
- /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
- /// (e.g. i64 -> i16). For types natively supported by the system, this holds
- /// the same type (e.g. i32 -> i32).
- MVT TransformToType[MVT::LAST_VALUETYPE];
-
- /// For each operation and each value type, keep a LegalizeAction that
- /// indicates how instruction selection should deal with the operation. Most
- /// operations are Legal (aka, supported natively by the target), but
- /// operations that are not should be described. Note that operations on
- /// non-legal value types are not described here.
- LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
-
- /// For each load extension type and each value type, keep a LegalizeAction
- /// that indicates how instruction selection should deal with a load of a
- /// specific value type and extension type. Uses 4-bits to store the action
- /// for each of the 4 load ext types.
- uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
-
- /// For each value type pair keep a LegalizeAction that indicates whether a
- /// truncating store of a specific value type and truncating type is legal.
- LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
-
- /// For each indexed mode and each value type, keep a pair of LegalizeAction
- /// that indicates how instruction selection should deal with the load /
- /// store.
- ///
- /// The first dimension is the value_type for the reference. The second
- /// dimension represents the various modes for load store.
- uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
-
- /// For each condition code (ISD::CondCode) keep a LegalizeAction that
- /// indicates how instruction selection should deal with the condition code.
- ///
- /// Because each CC action takes up 4 bits, we need to have the array size be
- /// large enough to fit all of the value types. This can be done by rounding
- /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
- uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
-
-protected:
- ValueTypeActionImpl ValueTypeActions;
-
-private:
- LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
-
- /// Targets can specify ISD nodes that they would like PerformDAGCombine
- /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
- /// array.
- unsigned char
- TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
-
- /// For operations that must be promoted to a specific type, this holds the
- /// destination type. This map should be sparse, so don't hold it as an
- /// array.
- ///
- /// Targets add entries to this map with AddPromotedToType(..), clients access
- /// this with getTypeToPromoteTo(..).
- std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
- PromoteToType;
-
- /// Stores the name each libcall.
- const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
-
- /// The ISD::CondCode that should be used to test the result of each of the
- /// comparison libcall against zero.
- ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
-
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
-
-protected:
- /// Return true if the extension represented by \p I is free.
- /// \pre \p I is a sign, zero, or fp extension and
- /// is[Z|FP]ExtFree of the related types is not true.
- virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
-
- /// Depth that GatherAllAliases should should continue looking for chain
- /// dependencies when trying to find a more preferable chain. As an
- /// approximation, this should be more than the number of consecutive stores
- /// expected to be merged.
- unsigned GatherAllAliasesMaxDepth;
-
- /// \brief Specify maximum number of store instructions per memset call.
- ///
- /// When lowering \@llvm.memset this field specifies the maximum number of
- /// store operations that may be substituted for the call to memset. Targets
- /// must set this value based on the cost threshold for that target. Targets
- /// should assume that the memset will be done using as many of the largest
- /// store operations first, followed by smaller ones, if necessary, per
- /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
- /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
- /// store. This only applies to setting a constant array of a constant size.
- unsigned MaxStoresPerMemset;
-
- /// Maximum number of stores operations that may be substituted for the call
- /// to memset, used for functions with OptSize attribute.
- unsigned MaxStoresPerMemsetOptSize;
-
- /// \brief Specify maximum bytes of store instructions per memcpy call.
- ///
- /// When lowering \@llvm.memcpy this field specifies the maximum number of
- /// store operations that may be substituted for a call to memcpy. Targets
- /// must set this value based on the cost threshold for that target. Targets
- /// should assume that the memcpy will be done using as many of the largest
- /// store operations first, followed by smaller ones, if necessary, per
- /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
- /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
- /// and one 1-byte store. This only applies to copying a constant array of
- /// constant size.
- unsigned MaxStoresPerMemcpy;
-
- /// Maximum number of store operations that may be substituted for a call to
- /// memcpy, used for functions with OptSize attribute.
- unsigned MaxStoresPerMemcpyOptSize;
- unsigned MaxLoadsPerMemcmp;
- unsigned MaxLoadsPerMemcmpOptSize;
-
- /// \brief Specify maximum bytes of store instructions per memmove call.
- ///
- /// When lowering \@llvm.memmove this field specifies the maximum number of
- /// store instructions that may be substituted for a call to memmove. Targets
- /// must set this value based on the cost threshold for that target. Targets
- /// should assume that the memmove will be done using as many of the largest
- /// store operations first, followed by smaller ones, if necessary, per
- /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
- /// with 8-bit alignment would result in nine 1-byte stores. This only
- /// applies to copying a constant array of constant size.
- unsigned MaxStoresPerMemmove;
-
- /// Maximum number of store instructions that may be substituted for a call to
- /// memmove, used for functions with OptSize attribute.
- unsigned MaxStoresPerMemmoveOptSize;
-
- /// Tells the code generator that select is more expensive than a branch if
- /// the branch is usually predicted right.
- bool PredictableSelectIsExpensive;
-
- /// \see enableExtLdPromotion.
- bool EnableExtLdPromotion;
-
- /// Return true if the value types that can be represented by the specified
- /// register class are all legal.
- bool isLegalRC(const TargetRegisterInfo &TRI,
- const TargetRegisterClass &RC) const;
-
- /// Replace/modify any TargetFrameIndex operands with a targte-dependent
- /// sequence of memory operands that is recognized by PrologEpilogInserter.
- MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
- MachineBasicBlock *MBB) const;
-};
-
-/// This class defines information used to lower LLVM code to legal SelectionDAG
-/// operators that the target instruction selector can accept natively.
-///
-/// This class also defines callbacks that targets must implement to lower
-/// target-specific constructs to SelectionDAG operators.
-class TargetLowering : public TargetLoweringBase {
-public:
- struct DAGCombinerInfo;
-
- TargetLowering(const TargetLowering &) = delete;
- TargetLowering &operator=(const TargetLowering &) = delete;
-
- /// NOTE: The TargetMachine owns TLOF.
- explicit TargetLowering(const TargetMachine &TM);
-
- bool isPositionIndependent() const;
-
- /// Returns true by value, base pointer and offset pointer and addressing mode
- /// by reference if the node's address can be legally represented as
- /// pre-indexed load / store address.
- virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
- SDValue &/*Offset*/,
- ISD::MemIndexedMode &/*AM*/,
- SelectionDAG &/*DAG*/) const {
- return false;
- }
-
- /// Returns true by value, base pointer and offset pointer and addressing mode
- /// by reference if this node can be combined with a load / store to form a
- /// post-indexed load / store.
- virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
- SDValue &/*Base*/,
- SDValue &/*Offset*/,
- ISD::MemIndexedMode &/*AM*/,
- SelectionDAG &/*DAG*/) const {
- return false;
- }
-
- /// Return the entry encoding for a jump table in the current function. The
- /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
- virtual unsigned getJumpTableEncoding() const;
-
- virtual const MCExpr *
- LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
- const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
- MCContext &/*Ctx*/) const {
- llvm_unreachable("Need to implement this hook if target has custom JTIs");
- }
-
- /// Returns relocation base for the given PIC jumptable.
- virtual SDValue getPICJumpTableRelocBase(SDValue Table,
- SelectionDAG &DAG) const;
-
- /// This returns the relocation base for the given PIC jumptable, the same as
- /// getPICJumpTableRelocBase, but as an MCExpr.
- virtual const MCExpr *
- getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
- unsigned JTI, MCContext &Ctx) const;
-
- /// Return true if folding a constant offset with the given GlobalAddress is
- /// legal. It is frequently not legal in PIC relocation models.
- virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
-
- bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
- SDValue &Chain) const;
-
- void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
- SDValue &NewRHS, ISD::CondCode &CCCode,
- const SDLoc &DL) const;
-
- /// Returns a pair of (return value, chain).
- /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
- std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
- EVT RetVT, ArrayRef<SDValue> Ops,
- bool isSigned, const SDLoc &dl,
- bool doesNotReturn = false,
- bool isReturnValueUsed = true) const;
-
- /// Check whether parameters to a call that are passed in callee saved
- /// registers are the same as from the calling function. This needs to be
- /// checked for tail call eligibility.
- bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
- const uint32_t *CallerPreservedMask,
- const SmallVectorImpl<CCValAssign> &ArgLocs,
- const SmallVectorImpl<SDValue> &OutVals) const;
-
- //===--------------------------------------------------------------------===//
- // TargetLowering Optimization Methods
- //
-
- /// A convenience struct that encapsulates a DAG, and two SDValues for
- /// returning information from TargetLowering to its clients that want to
- /// combine.
- struct TargetLoweringOpt {
- SelectionDAG &DAG;
- bool LegalTys;
- bool LegalOps;
- SDValue Old;
- SDValue New;
-
- explicit TargetLoweringOpt(SelectionDAG &InDAG,
- bool LT, bool LO) :
- DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
-
- bool LegalTypes() const { return LegalTys; }
- bool LegalOperations() const { return LegalOps; }
-
- bool CombineTo(SDValue O, SDValue N) {
- Old = O;
- New = N;
- return true;
- }
- };
-
- /// Check to see if the specified operand of the specified instruction is a
- /// constant integer. If so, check to see if there are any bits set in the
- /// constant that are not demanded. If so, shrink the constant and return
- /// true.
- bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
- TargetLoweringOpt &TLO) const;
-
- // Target hook to do target-specific const optimization, which is called by
- // ShrinkDemandedConstant. This function should return true if the target
- // doesn't want ShrinkDemandedConstant to further optimize the constant.
- virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
- TargetLoweringOpt &TLO) const {
- return false;
- }
-
- /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
- /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
- /// generalized for targets with other types of implicit widening casts.
- bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
- TargetLoweringOpt &TLO) const;
-
- /// Helper for SimplifyDemandedBits that can simplify an operation with
- /// multiple uses. This function simplifies operand \p OpIdx of \p User and
- /// then updates \p User with the simplified version. No other uses of
- /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
- /// function behaves exactly like function SimplifyDemandedBits declared
- /// below except that it also updates the DAG by calling
- /// DCI.CommitTargetLoweringOpt.
- bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
- DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
-
- /// Look at Op. At this point, we know that only the DemandedMask bits of the
- /// result of Op are ever used downstream. If we can use this information to
- /// simplify Op, create a new simplified DAG node and return true, returning
- /// the original and new nodes in Old and New. Otherwise, analyze the
- /// expression and return a mask of KnownOne and KnownZero bits for the
- /// expression (used to simplify the caller). The KnownZero/One bits may only
- /// be accurate for those bits in the DemandedMask.
- /// \p AssumeSingleUse When this parameter is true, this function will
- /// attempt to simplify \p Op even if there are multiple uses.
- /// Callers are responsible for correctly updating the DAG based on the
- /// results of this function, because simply replacing replacing TLO.Old
- /// with TLO.New will be incorrect when this parameter is true and TLO.Old
- /// has multiple uses.
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
- KnownBits &Known,
- TargetLoweringOpt &TLO,
- unsigned Depth = 0,
- bool AssumeSingleUse = false) const;
-
- /// Helper wrapper around SimplifyDemandedBits
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
- DAGCombinerInfo &DCI) const;
-
- /// Determine which of the bits specified in Mask are known to be either zero
- /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
- /// argument allows us to only collect the known bits that are shared by the
- /// requested vector elements.
- virtual void computeKnownBitsForTargetNode(const SDValue Op,
- KnownBits &Known,
- const APInt &DemandedElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
- /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
- /// Default implementation computes low bits based on alignment
- /// information. This should preserve known bits passed into it.
- virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
- KnownBits &Known,
- const APInt &DemandedElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
- /// This method can be implemented by targets that want to expose additional
- /// information about sign bits to the DAG Combiner. The DemandedElts
- /// argument allows us to only collect the minimum sign bits that are shared
- /// by the requested vector elements.
- virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
- const APInt &DemandedElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
- struct DAGCombinerInfo {
- void *DC; // The DAG Combiner object.
- CombineLevel Level;
- bool CalledByLegalizer;
-
- public:
- SelectionDAG &DAG;
-
- DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
- : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
-
- bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
- bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
- bool isAfterLegalizeVectorOps() const {
- return Level == AfterLegalizeDAG;
- }
- CombineLevel getDAGCombineLevel() { return Level; }
- bool isCalledByLegalizer() const { return CalledByLegalizer; }
-
- void AddToWorklist(SDNode *N);
- SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
- SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
- SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
-
- void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
- };
-
- /// Return if the N is a constant or constant vector equal to the true value
- /// from getBooleanContents().
- bool isConstTrueVal(const SDNode *N) const;
-
- /// Return if the N is a constant or constant vector equal to the false value
- /// from getBooleanContents().
- bool isConstFalseVal(const SDNode *N) const;
-
- /// Return a constant of type VT that contains a true value that respects
- /// getBooleanContents()
- SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
-
- /// Return if \p N is a True value when extended to \p VT.
- bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
-
- /// Try to simplify a setcc built with the specified operands and cc. If it is
- /// unable to simplify it, return a null SDValue.
- SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
- bool foldBooleans, DAGCombinerInfo &DCI,
- const SDLoc &dl) const;
-
- // For targets which wrap address, unwrap for analysis.
- virtual SDValue unwrapAddress(SDValue N) const { return N; }
-
- /// Returns true (and the GlobalValue and the offset) if the node is a
- /// GlobalAddress + offset.
- virtual bool
- isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
-
- /// This method will be invoked for all target nodes and for any
- /// target-independent nodes that the target has registered with invoke it
- /// for.
- ///
- /// The semantics are as follows:
- /// Return Value:
- /// SDValue.Val == 0 - No change was made
- /// SDValue.Val == N - N was replaced, is dead, and is already handled.
- /// otherwise - N should be replaced by the returned Operand.
- ///
- /// In addition, methods provided by DAGCombinerInfo may be used to perform
- /// more complex transformations.
- ///
- virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
-
- /// Return true if it is profitable to move a following shift through this
- // node, adjusting any immediate operands as necessary to preserve semantics.
- // This transformation may not be desirable if it disrupts a particularly
- // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
- // By default, it returns true.
- virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
- return true;
- }
-
- // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
- // to a shuffle and a truncate.
- // Example of such a combine:
- // v4i32 build_vector((extract_elt V, 1),
- // (extract_elt V, 3),
- // (extract_elt V, 5),
- // (extract_elt V, 7))
- // -->
- // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
- virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
- ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
- return false;
- }
-
- /// Return true if the target has native support for the specified value type
- /// and it is 'desirable' to use the type for the given node type. e.g. On x86
- /// i16 is legal, but undesirable since i16 instruction encodings are longer
- /// and some i16 instructions are slow.
- virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
- // By default, assume all legal types are desirable.
- return isTypeLegal(VT);
- }
-
- /// Return true if it is profitable for dag combiner to transform a floating
- /// point op of specified opcode to a equivalent op of an integer
- /// type. e.g. f32 load -> i32 load can be profitable on ARM.
- virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
- EVT /*VT*/) const {
- return false;
- }
-
- /// This method query the target whether it is beneficial for dag combiner to
- /// promote the specified node. If true, it should return the desired
- /// promotion type by reference.
- virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
- return false;
- }
-
- /// Return true if the target supports swifterror attribute. It optimizes
- /// loads and stores to reading and writing a specific register.
- virtual bool supportSwiftError() const {
- return false;
- }
-
- /// Return true if the target supports that a subset of CSRs for the given
- /// machine function is handled explicitly via copies.
- virtual bool supportSplitCSR(MachineFunction *MF) const {
- return false;
- }
-
- /// Perform necessary initialization to handle a subset of CSRs explicitly
- /// via copies. This function is called at the beginning of instruction
- /// selection.
- virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
- llvm_unreachable("Not Implemented");
- }
-
- /// Insert explicit copies in entry and exit blocks. We copy a subset of
- /// CSRs to virtual registers in the entry block, and copy them back to
- /// physical registers in the exit blocks. This function is called at the end
- /// of instruction selection.
- virtual void insertCopiesSplitCSR(
- MachineBasicBlock *Entry,
- const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
- llvm_unreachable("Not Implemented");
- }
-
- //===--------------------------------------------------------------------===//
- // Lowering methods - These methods must be implemented by targets so that
- // the SelectionDAGBuilder code knows how to lower these.
- //
-
- /// This hook must be implemented to lower the incoming (formal) arguments,
- /// described by the Ins array, into the specified DAG. The implementation
- /// should fill in the InVals array with legal-type argument values, and
- /// return the resulting token chain value.
- virtual SDValue LowerFormalArguments(
- SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
- const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
- SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
- llvm_unreachable("Not Implemented");
- }
-
- /// This structure contains all information that is necessary for lowering
- /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
- /// needs to lower a call, and targets will see this struct in their LowerCall
- /// implementation.
- struct CallLoweringInfo {
- SDValue Chain;
- Type *RetTy = nullptr;
- bool RetSExt : 1;
- bool RetZExt : 1;
- bool IsVarArg : 1;
- bool IsInReg : 1;
- bool DoesNotReturn : 1;
- bool IsReturnValueUsed : 1;
- bool IsConvergent : 1;
- bool IsPatchPoint : 1;
-
- // IsTailCall should be modified by implementations of
- // TargetLowering::LowerCall that perform tail call conversions.
- bool IsTailCall = false;
-
- // Is Call lowering done post SelectionDAG type legalization.
- bool IsPostTypeLegalization = false;
-
- unsigned NumFixedArgs = -1;
- CallingConv::ID CallConv = CallingConv::C;
- SDValue Callee;
- ArgListTy Args;
- SelectionDAG &DAG;
- SDLoc DL;
- ImmutableCallSite CS;
- SmallVector<ISD::OutputArg, 32> Outs;
- SmallVector<SDValue, 32> OutVals;
- SmallVector<ISD::InputArg, 32> Ins;
- SmallVector<SDValue, 4> InVals;
-
- CallLoweringInfo(SelectionDAG &DAG)
- : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
- DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
- IsPatchPoint(false), DAG(DAG) {}
-
- CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
- DL = dl;
- return *this;
- }
-
- CallLoweringInfo &setChain(SDValue InChain) {
- Chain = InChain;
- return *this;
- }
-
- // setCallee with target/module-specific attributes
- CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
- SDValue Target, ArgListTy &&ArgsList) {
- RetTy = ResultType;
- Callee = Target;
- CallConv = CC;
- NumFixedArgs = ArgsList.size();
- Args = std::move(ArgsList);
-
- DAG.getTargetLoweringInfo().markLibCallAttributes(
- &(DAG.getMachineFunction()), CC, Args);
- return *this;
- }
-
- CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
- SDValue Target, ArgListTy &&ArgsList) {
- RetTy = ResultType;
- Callee = Target;
- CallConv = CC;
- NumFixedArgs = ArgsList.size();
- Args = std::move(ArgsList);
- return *this;
- }
-
- CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
- SDValue Target, ArgListTy &&ArgsList,
- ImmutableCallSite Call) {
- RetTy = ResultType;
-
- IsInReg = Call.hasRetAttr(Attribute::InReg);
- DoesNotReturn =
- Call.doesNotReturn() ||
- (!Call.isInvoke() &&
- isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
- IsVarArg = FTy->isVarArg();
- IsReturnValueUsed = !Call.getInstruction()->use_empty();
- RetSExt = Call.hasRetAttr(Attribute::SExt);
- RetZExt = Call.hasRetAttr(Attribute::ZExt);
-
- Callee = Target;
-
- CallConv = Call.getCallingConv();
- NumFixedArgs = FTy->getNumParams();
- Args = std::move(ArgsList);
-
- CS = Call;
-
- return *this;
- }
-
- CallLoweringInfo &setInRegister(bool Value = true) {
- IsInReg = Value;
- return *this;
- }
-
- CallLoweringInfo &setNoReturn(bool Value = true) {
- DoesNotReturn = Value;
- return *this;
- }
-
- CallLoweringInfo &setVarArg(bool Value = true) {
- IsVarArg = Value;
- return *this;
- }
-
- CallLoweringInfo &setTailCall(bool Value = true) {
- IsTailCall = Value;
- return *this;
- }
-
- CallLoweringInfo &setDiscardResult(bool Value = true) {
- IsReturnValueUsed = !Value;
- return *this;
- }
-
- CallLoweringInfo &setConvergent(bool Value = true) {
- IsConvergent = Value;
- return *this;
- }
-
- CallLoweringInfo &setSExtResult(bool Value = true) {
- RetSExt = Value;
- return *this;
- }
-
- CallLoweringInfo &setZExtResult(bool Value = true) {
- RetZExt = Value;
- return *this;
- }
-
- CallLoweringInfo &setIsPatchPoint(bool Value = true) {
- IsPatchPoint = Value;
- return *this;
- }
-
- CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
- IsPostTypeLegalization = Value;
- return *this;
- }
-
- ArgListTy &getArgs() {
- return Args;
- }
- };
-
- /// This function lowers an abstract call to a function into an actual call.
- /// This returns a pair of operands. The first element is the return value
- /// for the function (if RetTy is not VoidTy). The second element is the
- /// outgoing token chain. It calls LowerCall to do the actual lowering.
- std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
-
- /// This hook must be implemented to lower calls into the specified
- /// DAG. The outgoing arguments to the call are described by the Outs array,
- /// and the values to be returned by the call are described by the Ins
- /// array. The implementation should fill in the InVals array with legal-type
- /// return values from the call, and return the resulting token chain value.
- virtual SDValue
- LowerCall(CallLoweringInfo &/*CLI*/,
- SmallVectorImpl<SDValue> &/*InVals*/) const {
- llvm_unreachable("Not Implemented");
- }
-
- /// Target-specific cleanup for formal ByVal parameters.
- virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
-
- /// This hook should be implemented to check whether the return values
- /// described by the Outs array can fit into the return registers. If false
- /// is returned, an sret-demotion is performed.
- virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
- MachineFunction &/*MF*/, bool /*isVarArg*/,
- const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
- LLVMContext &/*Context*/) const
- {
- // Return true by default to get preexisting behavior.
- return true;
- }
-
- /// This hook must be implemented to lower outgoing return values, described
- /// by the Outs array, into the specified DAG. The implementation should
- /// return the resulting token chain value.
- virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
- bool /*isVarArg*/,
- const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
- const SmallVectorImpl<SDValue> & /*OutVals*/,
- const SDLoc & /*dl*/,
- SelectionDAG & /*DAG*/) const {
- llvm_unreachable("Not Implemented");
- }
-
- /// Return true if result of the specified node is used by a return node
- /// only. It also compute and return the input chain for the tail call.
- ///
- /// This is used to determine whether it is possible to codegen a libcall as
- /// tail call at legalization time.
- virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
- return false;
- }
-
- /// Return true if the target may be able emit the call instruction as a tail
- /// call. This is used by optimization passes to determine if it's profitable
- /// to duplicate return instructions to enable tailcall optimization.
- virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
- return false;
- }
-
- /// Return the builtin name for the __builtin___clear_cache intrinsic
- /// Default is to invoke the clear cache library call
- virtual const char * getClearCacheBuiltinName() const {
- return "__clear_cache";
- }
-
- /// Return the register ID of the name passed in. Used by named register
- /// global variables extension. There is no target-independent behaviour
- /// so the default action is to bail.
- virtual unsigned getRegisterByName(const char* RegName, EVT VT,
- SelectionDAG &DAG) const {
- report_fatal_error("Named registers not implemented for this target");
- }
-
- /// Return the type that should be used to zero or sign extend a
- /// zeroext/signext integer return value. FIXME: Some C calling conventions
- /// require the return type to be promoted, but this is not true all the time,
- /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
- /// conventions. The frontend should handle this and include all of the
- /// necessary information.
- virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
- ISD::NodeType /*ExtendKind*/) const {
- EVT MinVT = getRegisterType(Context, MVT::i32);
- return VT.bitsLT(MinVT) ? MinVT : VT;
- }
-
- /// For some targets, an LLVM struct type must be broken down into multiple
- /// simple types, but the calling convention specifies that the entire struct
- /// must be passed in a block of consecutive registers.
- virtual bool
- functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
- bool isVarArg) const {
- return false;
- }
-
- /// Returns a 0 terminated array of registers that can be safely used as
- /// scratch registers.
- virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
- return nullptr;
- }
-
- /// This callback is used to prepare for a volatile or atomic load.
- /// It takes a chain node as input and returns the chain for the load itself.
- ///
- /// Having a callback like this is necessary for targets like SystemZ,
- /// which allows a CPU to reuse the result of a previous load indefinitely,
- /// even if a cache-coherent store is performed by another CPU. The default
- /// implementation does nothing.
- virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
- SelectionDAG &DAG) const {
- return Chain;
- }
-
- /// This callback is used to inspect load/store instructions and add
- /// target-specific MachineMemOperand flags to them. The default
- /// implementation does nothing.
- virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
- return MachineMemOperand::MONone;
- }
-
- /// This callback is invoked by the type legalizer to legalize nodes with an
- /// illegal operand type but legal result types. It replaces the
- /// LowerOperation callback in the type Legalizer. The reason we can not do
- /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
- /// use this callback.
- ///
- /// TODO: Consider merging with ReplaceNodeResults.
- ///
- /// The target places new result values for the node in Results (their number
- /// and types must exactly match those of the original return values of
- /// the node), or leaves Results empty, which indicates that the node is not
- /// to be custom lowered after all.
- /// The default implementation calls LowerOperation.
- virtual void LowerOperationWrapper(SDNode *N,
- SmallVectorImpl<SDValue> &Results,
- SelectionDAG &DAG) const;
-
- /// This callback is invoked for operations that are unsupported by the
- /// target, which are registered to use 'custom' lowering, and whose defined
- /// values are all legal. If the target has no operations that require custom
- /// lowering, it need not implement this. The default implementation of this
- /// aborts.
- virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-
- /// This callback is invoked when a node result type is illegal for the
- /// target, and the operation was registered to use 'custom' lowering for that
- /// result type. The target places new result values for the node in Results
- /// (their number and types must exactly match those of the original return
- /// values of the node), or leaves Results empty, which indicates that the
- /// node is not to be custom lowered after all.
- ///
- /// If the target has no operations that require custom lowering, it need not
- /// implement this. The default implementation aborts.
- virtual void ReplaceNodeResults(SDNode * /*N*/,
- SmallVectorImpl<SDValue> &/*Results*/,
- SelectionDAG &/*DAG*/) const {
- llvm_unreachable("ReplaceNodeResults not implemented for this target!");
- }
-
- /// This method returns the name of a target specific DAG node.
- virtual const char *getTargetNodeName(unsigned Opcode) const;
-
- /// This method returns a target specific FastISel object, or null if the
- /// target does not support "fast" ISel.
- virtual FastISel *createFastISel(FunctionLoweringInfo &,
- const TargetLibraryInfo *) const {
- return nullptr;
- }
-
- bool verifyReturnAddressArgumentIsConstant(SDValue Op,
- SelectionDAG &DAG) const;
-
- //===--------------------------------------------------------------------===//
- // Inline Asm Support hooks
- //
-
- /// This hook allows the target to expand an inline asm call to be explicit
- /// llvm code if it wants to. This is useful for turning simple inline asms
- /// into LLVM intrinsics, which gives the compiler more information about the
- /// behavior of the code.
- virtual bool ExpandInlineAsm(CallInst *) const {
- return false;
- }
-
- enum ConstraintType {
- C_Register, // Constraint represents specific register(s).
- C_RegisterClass, // Constraint represents any of register(s) in class.
- C_Memory, // Memory constraint.
- C_Other, // Something else.
- C_Unknown // Unsupported constraint.
- };
-
- enum ConstraintWeight {
- // Generic weights.
- CW_Invalid = -1, // No match.
- CW_Okay = 0, // Acceptable.
- CW_Good = 1, // Good weight.
- CW_Better = 2, // Better weight.
- CW_Best = 3, // Best weight.
-
- // Well-known weights.
- CW_SpecificReg = CW_Okay, // Specific register operands.
- CW_Register = CW_Good, // Register operands.
- CW_Memory = CW_Better, // Memory operands.
- CW_Constant = CW_Best, // Constant operand.
- CW_Default = CW_Okay // Default or don't know type.
- };
-
- /// This contains information for each constraint that we are lowering.
- struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
- /// This contains the actual string for the code, like "m". TargetLowering
- /// picks the 'best' code from ConstraintInfo::Codes that most closely
- /// matches the operand.
- std::string ConstraintCode;
-
- /// Information about the constraint code, e.g. Register, RegisterClass,
- /// Memory, Other, Unknown.
- TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
-
- /// If this is the result output operand or a clobber, this is null,
- /// otherwise it is the incoming operand to the CallInst. This gets
- /// modified as the asm is processed.
- Value *CallOperandVal = nullptr;
-
- /// The ValueType for the operand value.
- MVT ConstraintVT = MVT::Other;
-
- /// Copy constructor for copying from a ConstraintInfo.
- AsmOperandInfo(InlineAsm::ConstraintInfo Info)
- : InlineAsm::ConstraintInfo(std::move(Info)) {}
-
- /// Return true of this is an input operand that is a matching constraint
- /// like "4".
- bool isMatchingInputConstraint() const;
-
- /// If this is an input matching constraint, this method returns the output
- /// operand it matches.
- unsigned getMatchedOperand() const;
- };
-
- using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
-
- /// Split up the constraint string from the inline assembly value into the
- /// specific constraints and their prefixes, and also tie in the associated
- /// operand values. If this returns an empty vector, and if the constraint
- /// string itself isn't empty, there was an error parsing.
- virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
- const TargetRegisterInfo *TRI,
- ImmutableCallSite CS) const;
-
- /// Examine constraint type and operand type and determine a weight value.
- /// The operand object must already have been set up with the operand type.
- virtual ConstraintWeight getMultipleConstraintMatchWeight(
- AsmOperandInfo &info, int maIndex) const;
-
- /// Examine constraint string and operand type and determine a weight value.
- /// The operand object must already have been set up with the operand type.
- virtual ConstraintWeight getSingleConstraintMatchWeight(
- AsmOperandInfo &info, const char *constraint) const;
-
- /// Determines the constraint code and constraint type to use for the specific
- /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
- /// If the actual operand being passed in is available, it can be passed in as
- /// Op, otherwise an empty SDValue can be passed.
- virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
- SDValue Op,
- SelectionDAG *DAG = nullptr) const;
-
- /// Given a constraint, return the type of constraint it is for this target.
- virtual ConstraintType getConstraintType(StringRef Constraint) const;
-
- /// Given a physical register constraint (e.g. {edx}), return the register
- /// number and the register class for the register.
- ///
- /// Given a register class constraint, like 'r', if this corresponds directly
- /// to an LLVM register class, return a register of 0 and the register class
- /// pointer.
- ///
- /// This should only be used for C_Register constraints. On error, this
- /// returns a register number of 0 and a null register class pointer.
- virtual std::pair<unsigned, const TargetRegisterClass *>
- getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
- StringRef Constraint, MVT VT) const;
-
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
- if (ConstraintCode == "i")
- return InlineAsm::Constraint_i;
- else if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
- return InlineAsm::Constraint_Unknown;
- }
-
- /// Try to replace an X constraint, which matches anything, with another that
- /// has more specific requirements based on the type of the corresponding
- /// operand. This returns null if there is no replacement to make.
- virtual const char *LowerXConstraint(EVT ConstraintVT) const;
-
- /// Lower the specified operand into the Ops vector. If it is invalid, don't
- /// add anything to Ops.
- virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
- std::vector<SDValue> &Ops,
- SelectionDAG &DAG) const;
-
- //===--------------------------------------------------------------------===//
- // Div utility functions
- //
- SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
- bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
- SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
- bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
-
- /// Targets may override this function to provide custom SDIV lowering for
- /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
- /// assumes SDIV is expensive and replaces it with a series of other integer
- /// operations.
- virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
- SelectionDAG &DAG,
- std::vector<SDNode *> *Created) const;
-
- /// Indicate whether this target prefers to combine FDIVs with the same
- /// divisor. If the transform should never be done, return zero. If the
- /// transform should be done, return the minimum number of divisor uses
- /// that must exist.
- virtual unsigned combineRepeatedFPDivisors() const {
- return 0;
- }
-
- /// Hooks for building estimates in place of slower divisions and square
- /// roots.
-
- /// Return either a square root or its reciprocal estimate value for the input
- /// operand.
- /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
- /// 'Enabled' as set by a potential default override attribute.
- /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
- /// refinement iterations required to generate a sufficient (though not
- /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
- /// The boolean UseOneConstNR output is used to select a Newton-Raphson
- /// algorithm implementation that uses either one or two constants.
- /// The boolean Reciprocal is used to select whether the estimate is for the
- /// square root of the input operand or the reciprocal of its square root.
- /// A target may choose to implement its own refinement within this function.
- /// If that's true, then return '0' as the number of RefinementSteps to avoid
- /// any further refinement of the estimate.
- /// An empty SDValue return means no estimate sequence can be created.
- virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
- int Enabled, int &RefinementSteps,
- bool &UseOneConstNR, bool Reciprocal) const {
- return SDValue();
- }
-
- /// Return a reciprocal estimate value for the input operand.
- /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
- /// 'Enabled' as set by a potential default override attribute.
- /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
- /// refinement iterations required to generate a sufficient (though not
- /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
- /// A target may choose to implement its own refinement within this function.
- /// If that's true, then return '0' as the number of RefinementSteps to avoid
- /// any further refinement of the estimate.
- /// An empty SDValue return means no estimate sequence can be created.
- virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
- int Enabled, int &RefinementSteps) const {
- return SDValue();
- }
-
- //===--------------------------------------------------------------------===//
- // Legalization utility functions
- //
-
- /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
- /// respectively, each computing an n/2-bit part of the result.
- /// \param Result A vector that will be filled with the parts of the result
- /// in little-endian order.
- /// \param LL Low bits of the LHS of the MUL. You can use this parameter
- /// if you want to control how low bits are extracted from the LHS.
- /// \param LH High bits of the LHS of the MUL. See LL for meaning.
- /// \param RL Low bits of the RHS of the MUL. See LL for meaning
- /// \param RH High bits of the RHS of the MUL. See LL for meaning.
- /// \returns true if the node has been expanded, false if it has not
- bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
- SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
- SelectionDAG &DAG, MulExpansionKind Kind,
- SDValue LL = SDValue(), SDValue LH = SDValue(),
- SDValue RL = SDValue(), SDValue RH = SDValue()) const;
-
- /// Expand a MUL into two nodes. One that computes the high bits of
- /// the result and one that computes the low bits.
- /// \param HiLoVT The value type to use for the Lo and Hi nodes.
- /// \param LL Low bits of the LHS of the MUL. You can use this parameter
- /// if you want to control how low bits are extracted from the LHS.
- /// \param LH High bits of the LHS of the MUL. See LL for meaning.
- /// \param RL Low bits of the RHS of the MUL. See LL for meaning
- /// \param RH High bits of the RHS of the MUL. See LL for meaning.
- /// \returns true if the node has been expanded. false if it has not
- bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
- SelectionDAG &DAG, MulExpansionKind Kind,
- SDValue LL = SDValue(), SDValue LH = SDValue(),
- SDValue RL = SDValue(), SDValue RH = SDValue()) const;
-
- /// Expand float(f32) to SINT(i64) conversion
- /// \param N Node to expand
- /// \param Result output after conversion
- /// \returns True, if the expansion was successful, false otherwise
- bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
-
- /// Turn load of vector type into a load of the individual elements.
- /// \param LD load to expand
- /// \returns MERGE_VALUEs of the scalar loads with their chains.
- SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
-
- // Turn a store of a vector type into stores of the individual elements.
- /// \param ST Store with a vector value type
- /// \returns MERGE_VALUs of the individual store chains.
- SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
-
- /// Expands an unaligned load to 2 half-size loads for an integer, and
- /// possibly more for vectors.
- std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
- SelectionDAG &DAG) const;
-
- /// Expands an unaligned store to 2 half-size stores for integer values, and
- /// possibly more for vectors.
- SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
-
- /// Increments memory address \p Addr according to the type of the value
- /// \p DataVT that should be stored. If the data is stored in compressed
- /// form, the memory address should be incremented according to the number of
- /// the stored elements. This number is equal to the number of '1's bits
- /// in the \p Mask.
- /// \p DataVT is a vector type. \p Mask is a vector value.
- /// \p DataVT and \p Mask have the same number of vector elements.
- SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
- EVT DataVT, SelectionDAG &DAG,
- bool IsCompressedMemory) const;
-
- /// Get a pointer to vector element \p Idx located in memory for a vector of
- /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
- /// bounds the returned pointer is unspecified, but will be within the vector
- /// bounds.
- SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
- SDValue Idx) const;
-
- //===--------------------------------------------------------------------===//
- // Instruction Emitting Hooks
- //
-
- /// This method should be implemented by targets that mark instructions with
- /// the 'usesCustomInserter' flag. These instructions are special in various
- /// ways, which require special support to insert. The specified MachineInstr
- /// is created but not inserted into any basic blocks, and this method is
- /// called to expand it into a sequence of instructions, potentially also
- /// creating new basic blocks and control flow.
- /// As long as the returned basic block is different (i.e., we created a new
- /// one), the custom inserter is free to modify the rest of \p MBB.
- virtual MachineBasicBlock *
- EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
-
- /// This method should be implemented by targets that mark instructions with
- /// the 'hasPostISelHook' flag. These instructions must be adjusted after
- /// instruction selection by target hooks. e.g. To fill in optional defs for
- /// ARM 's' setting instructions.
- virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
- SDNode *Node) const;
-
- /// If this function returns true, SelectionDAGBuilder emits a
- /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
- virtual bool useLoadStackGuardNode() const {
- return false;
- }
-
- /// Lower TLS global address SDNode for target independent emulated TLS model.
- virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
- SelectionDAG &DAG) const;
-
- // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
- // If we're comparing for equality to zero and isCtlzFast is true, expose the
- // fact that this can be implemented as a ctlz/srl pair, so that the dag
- // combiner can fold the new nodes.
- SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
-
-private:
- SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
- ISD::CondCode Cond, DAGCombinerInfo &DCI,
- const SDLoc &DL) const;
-};
-
-/// Given an LLVM IR type and return type attributes, compute the return value
-/// EVTs and flags, and optionally also the offsets, if the return value is
-/// being lowered to memory.
-void GetReturnInfo(Type *ReturnType, AttributeList attr,
- SmallVectorImpl<ISD::OutputArg> &Outs,
- const TargetLowering &TLI, const DataLayout &DL);
-
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETLOWERING_H
Removed: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (removed)
@@ -1,194 +0,0 @@
-//===-- llvm/Target/TargetLoweringObjectFile.h - Object Info ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements classes used to handle lowerings specific to common
-// object file formats.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
-#define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/MCObjectFileInfo.h"
-#include "llvm/MC/SectionKind.h"
-#include <cstdint>
-
-namespace llvm {
-
-class GlobalValue;
-class MachineModuleInfo;
-class Mangler;
-class MCContext;
-class MCExpr;
-class MCSection;
-class MCSymbol;
-class MCSymbolRefExpr;
-class MCStreamer;
-class MCValue;
-class TargetMachine;
-
-class TargetLoweringObjectFile : public MCObjectFileInfo {
- MCContext *Ctx = nullptr;
-
- /// Name-mangler for global names.
- Mangler *Mang = nullptr;
-
-protected:
- bool SupportIndirectSymViaGOTPCRel = false;
- bool SupportGOTPCRelWithOffset = true;
-
- /// This section contains the static constructor pointer list.
- MCSection *StaticCtorSection = nullptr;
-
- /// This section contains the static destructor pointer list.
- MCSection *StaticDtorSection = nullptr;
-
-public:
- TargetLoweringObjectFile() = default;
- TargetLoweringObjectFile(const TargetLoweringObjectFile &) = delete;
- TargetLoweringObjectFile &
- operator=(const TargetLoweringObjectFile &) = delete;
- virtual ~TargetLoweringObjectFile();
-
- MCContext &getContext() const { return *Ctx; }
- Mangler &getMangler() const { return *Mang; }
-
- /// This method must be called before any actual lowering is done. This
- /// specifies the current context for codegen, and gives the lowering
- /// implementations a chance to set up their default sections.
- virtual void Initialize(MCContext &ctx, const TargetMachine &TM);
-
- virtual void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &TM,
- const MCSymbol *Sym) const;
-
- /// Emit the module-level metadata that the platform cares about.
- virtual void emitModuleMetadata(MCStreamer &Streamer, Module &M,
- const TargetMachine &TM) const {}
-
- /// Given a constant with the SectionKind, return a section that it should be
- /// placed in.
- virtual MCSection *getSectionForConstant(const DataLayout &DL,
- SectionKind Kind,
- const Constant *C,
- unsigned &Align) const;
-
- /// Classify the specified global variable into a set of target independent
- /// categories embodied in SectionKind.
- static SectionKind getKindForGlobal(const GlobalObject *GO,
- const TargetMachine &TM);
-
- /// This method computes the appropriate section to emit the specified global
- /// variable or function definition. This should not be passed external (or
- /// available externally) globals.
- MCSection *SectionForGlobal(const GlobalObject *GO, SectionKind Kind,
- const TargetMachine &TM) const;
-
- /// This method computes the appropriate section to emit the specified global
- /// variable or function definition. This should not be passed external (or
- /// available externally) globals.
- MCSection *SectionForGlobal(const GlobalObject *GO,
- const TargetMachine &TM) const {
- return SectionForGlobal(GO, getKindForGlobal(GO, TM), TM);
- }
-
- virtual void getNameWithPrefix(SmallVectorImpl<char> &OutName,
- const GlobalValue *GV,
- const TargetMachine &TM) const;
-
- virtual MCSection *getSectionForJumpTable(const Function &F,
- const TargetMachine &TM) const;
-
- virtual bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference,
- const Function &F) const;
-
- /// Targets should implement this method to assign a section to globals with
- /// an explicit section specfied. The implementation of this method can
- /// assume that GO->hasSection() is true.
- virtual MCSection *
- getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind,
- const TargetMachine &TM) const = 0;
-
- /// Return an MCExpr to use for a reference to the specified global variable
- /// from exception handling information.
- virtual const MCExpr *getTTypeGlobalReference(const GlobalValue *GV,
- unsigned Encoding,
- const TargetMachine &TM,
- MachineModuleInfo *MMI,
- MCStreamer &Streamer) const;
-
- /// Return the MCSymbol for a private symbol with global value name as its
- /// base, with the specified suffix.
- MCSymbol *getSymbolWithGlobalValueBase(const GlobalValue *GV,
- StringRef Suffix,
- const TargetMachine &TM) const;
-
- // The symbol that gets passed to .cfi_personality.
- virtual MCSymbol *getCFIPersonalitySymbol(const GlobalValue *GV,
- const TargetMachine &TM,
- MachineModuleInfo *MMI) const;
-
- const MCExpr *getTTypeReference(const MCSymbolRefExpr *Sym, unsigned Encoding,
- MCStreamer &Streamer) const;
-
- virtual MCSection *getStaticCtorSection(unsigned Priority,
- const MCSymbol *KeySym) const {
- return StaticCtorSection;
- }
-
- virtual MCSection *getStaticDtorSection(unsigned Priority,
- const MCSymbol *KeySym) const {
- return StaticDtorSection;
- }
-
- /// \brief Create a symbol reference to describe the given TLS variable when
- /// emitting the address in debug info.
- virtual const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const;
-
- virtual const MCExpr *lowerRelativeReference(const GlobalValue *LHS,
- const GlobalValue *RHS,
- const TargetMachine &TM) const {
- return nullptr;
- }
-
- /// \brief Target supports replacing a data "PC"-relative access to a symbol
- /// through another symbol, by accessing the later via a GOT entry instead?
- bool supportIndirectSymViaGOTPCRel() const {
- return SupportIndirectSymViaGOTPCRel;
- }
-
- /// \brief Target GOT "PC"-relative relocation supports encoding an additional
- /// binary expression with an offset?
- bool supportGOTPCRelWithOffset() const {
- return SupportGOTPCRelWithOffset;
- }
-
- /// \brief Get the target specific PC relative GOT entry relocation
- virtual const MCExpr *getIndirectSymViaGOTPCRel(const MCSymbol *Sym,
- const MCValue &MV,
- int64_t Offset,
- MachineModuleInfo *MMI,
- MCStreamer &Streamer) const {
- return nullptr;
- }
-
- virtual void emitLinkerFlagsForGlobal(raw_ostream &OS,
- const GlobalValue *GV) const {}
-
-protected:
- virtual MCSection *SelectSectionForGlobal(const GlobalObject *GO,
- SectionKind Kind,
- const TargetMachine &TM) const = 0;
-};
-
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
Removed: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def (removed)
@@ -1,442 +0,0 @@
-//===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target independent instruction opcodes.
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
-///
-#ifndef HANDLE_TARGET_OPCODE
-#define HANDLE_TARGET_OPCODE(OPC, NUM)
-#endif
-
-/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
-///
-#ifndef HANDLE_TARGET_OPCODE_MARKER
-#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
-#endif
-
-/// Every instruction defined here must also appear in Target.td.
-///
-HANDLE_TARGET_OPCODE(PHI)
-HANDLE_TARGET_OPCODE(INLINEASM)
-HANDLE_TARGET_OPCODE(CFI_INSTRUCTION)
-HANDLE_TARGET_OPCODE(EH_LABEL)
-HANDLE_TARGET_OPCODE(GC_LABEL)
-HANDLE_TARGET_OPCODE(ANNOTATION_LABEL)
-
-/// KILL - This instruction is a noop that is used only to adjust the
-/// liveness of registers. This can be useful when dealing with
-/// sub-registers.
-HANDLE_TARGET_OPCODE(KILL)
-
-/// EXTRACT_SUBREG - This instruction takes two operands: a register
-/// that has subregisters, and a subregister index. It returns the
-/// extracted subregister value. This is commonly used to implement
-/// truncation operations on target architectures which support it.
-HANDLE_TARGET_OPCODE(EXTRACT_SUBREG)
-
-/// INSERT_SUBREG - This instruction takes three operands: a register that
-/// has subregisters, a register providing an insert value, and a
-/// subregister index. It returns the value of the first register with the
-/// value of the second register inserted. The first register is often
-/// defined by an IMPLICIT_DEF, because it is commonly used to implement
-/// anyext operations on target architectures which support it.
-HANDLE_TARGET_OPCODE(INSERT_SUBREG)
-
-/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
-HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
-
-/// SUBREG_TO_REG - Assert the value of bits in a super register.
-/// The result of this instruction is the value of the second operand inserted
-/// into the subregister specified by the third operand. All other bits are
-/// assumed to be equal to the bits in the immediate integer constant in the
-/// first operand. This instruction just communicates information; No code
-/// should be generated.
-/// This is typically used after an instruction where the write to a subregister
-/// implicitly cleared the bits in the super registers.
-HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
-
-/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
-/// register-to-register copy into a specific register class. This is only
-/// used between instruction selection and MachineInstr creation, before
-/// virtual registers have been created for all the instructions, and it's
-/// only needed in cases where the register classes implied by the
-/// instructions are insufficient. It is emitted as a COPY MachineInstr.
- HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
-
-/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
-HANDLE_TARGET_OPCODE(DBG_VALUE)
-
-/// REG_SEQUENCE - This variadic instruction is used to form a register that
-/// represents a consecutive sequence of sub-registers. It's used as a
-/// register coalescing / allocation aid and must be eliminated before code
-/// emission.
-// In SDNode form, the first operand encodes the register class created by
-// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
-// pair. Once it has been lowered to a MachineInstr, the regclass operand
-// is no longer present.
-/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
-/// After register coalescing references of v1024 should be replace with
-/// v1027:3, v1025 with v1027:4, etc.
- HANDLE_TARGET_OPCODE(REG_SEQUENCE)
-
-/// COPY - Target-independent register copy. This instruction can also be
-/// used to copy between subregisters of virtual registers.
- HANDLE_TARGET_OPCODE(COPY)
-
-/// BUNDLE - This instruction represents an instruction bundle. Instructions
-/// which immediately follow a BUNDLE instruction which are marked with
-/// 'InsideBundle' flag are inside the bundle.
-HANDLE_TARGET_OPCODE(BUNDLE)
-
-/// Lifetime markers.
-HANDLE_TARGET_OPCODE(LIFETIME_START)
-HANDLE_TARGET_OPCODE(LIFETIME_END)
-
-/// A Stackmap instruction captures the location of live variables at its
-/// position in the instruction stream. It is followed by a shadow of bytes
-/// that must lie within the function and not contain another stackmap.
-HANDLE_TARGET_OPCODE(STACKMAP)
-
-/// FEntry all - This is a marker instruction which gets translated into a raw fentry call.
-HANDLE_TARGET_OPCODE(FENTRY_CALL)
-
-/// Patchable call instruction - this instruction represents a call to a
-/// constant address, followed by a series of NOPs. It is intended to
-/// support optimizations for dynamic languages (such as javascript) that
-/// rewrite calls to runtimes with more efficient code sequences.
-/// This also implies a stack map.
-HANDLE_TARGET_OPCODE(PATCHPOINT)
-
-/// This pseudo-instruction loads the stack guard value. Targets which need
-/// to prevent the stack guard value or address from being spilled to the
-/// stack should override TargetLowering::emitLoadStackGuardNode and
-/// additionally expand this pseudo after register allocation.
-HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
-
-/// Call instruction with associated vm state for deoptimization and list
-/// of live pointers for relocation by the garbage collector. It is
-/// intended to support garbage collection with fully precise relocating
-/// collectors and deoptimizations in either the callee or caller.
-HANDLE_TARGET_OPCODE(STATEPOINT)
-
-/// Instruction that records the offset of a local stack allocation passed to
-/// llvm.localescape. It has two arguments: the symbol for the label and the
-/// frame index of the local stack allocation.
-HANDLE_TARGET_OPCODE(LOCAL_ESCAPE)
-
-/// Wraps a machine instruction which can fault, bundled with associated
-/// information on how to handle such a fault.
-/// For example loading instruction that may page fault, bundled with associated
-/// information on how to handle such a page fault. It is intended to support
-/// "zero cost" null checks in managed languages by allowing LLVM to fold
-/// comparisons into existing memory operations.
-HANDLE_TARGET_OPCODE(FAULTING_OP)
-
-/// Wraps a machine instruction to add patchability constraints. An
-/// instruction wrapped in PATCHABLE_OP has to either have a minimum
-/// size or be preceded with a nop of that size. The first operand is
-/// an immediate denoting the minimum size of the instruction, the
-/// second operand is an immediate denoting the opcode of the original
-/// instruction. The rest of the operands are the operands of the
-/// original instruction.
-HANDLE_TARGET_OPCODE(PATCHABLE_OP)
-
-/// This is a marker instruction which gets translated into a nop sled, useful
-/// for inserting instrumentation instructions at runtime.
-HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER)
-
-/// Wraps a return instruction and its operands to enable adding nop sleds
-/// either before or after the return. The nop sleds are useful for inserting
-/// instrumentation instructions at runtime.
-/// The patch here replaces the return instruction.
-HANDLE_TARGET_OPCODE(PATCHABLE_RET)
-
-/// This is a marker instruction which gets translated into a nop sled, useful
-/// for inserting instrumentation instructions at runtime.
-/// The patch here prepends the return instruction.
-/// The same thing as in x86_64 is not possible for ARM because it has multiple
-/// return instructions. Furthermore, CPU allows parametrized and even
-/// conditional return instructions. In the current ARM implementation we are
-/// making use of the fact that currently LLVM doesn't seem to generate
-/// conditional return instructions.
-/// On ARM, the same instruction can be used for popping multiple registers
-/// from the stack and returning (it just pops pc register too), and LLVM
-/// generates it sometimes. So we can't insert the sled between this stack
-/// adjustment and the return without splitting the original instruction into 2
-/// instructions. So on ARM, rather than jumping into the exit trampoline, we
-/// call it, it does the tracing, preserves the stack and returns.
-HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT)
-
-/// Wraps a tail call instruction and its operands to enable adding nop sleds
-/// either before or after the tail exit. We use this as a disambiguation from
-/// PATCHABLE_RET which specifically only works for return instructions.
-HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL)
-
-/// Wraps a logging call and its arguments with nop sleds. At runtime, this can be
-/// patched to insert instrumentation instructions.
-HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
-
-/// The following generic opcodes are not supposed to appear after ISel.
-/// This is something we might want to relax, but for now, this is convenient
-/// to produce diagnostics.
-
-/// Generic ADD instruction. This is an integer add.
-HANDLE_TARGET_OPCODE(G_ADD)
-HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
-
-/// Generic SUB instruction. This is an integer sub.
-HANDLE_TARGET_OPCODE(G_SUB)
-
-// Generic multiply instruction.
-HANDLE_TARGET_OPCODE(G_MUL)
-
-// Generic signed division instruction.
-HANDLE_TARGET_OPCODE(G_SDIV)
-
-// Generic unsigned division instruction.
-HANDLE_TARGET_OPCODE(G_UDIV)
-
-// Generic signed remainder instruction.
-HANDLE_TARGET_OPCODE(G_SREM)
-
-// Generic unsigned remainder instruction.
-HANDLE_TARGET_OPCODE(G_UREM)
-
-/// Generic bitwise and instruction.
-HANDLE_TARGET_OPCODE(G_AND)
-
-/// Generic bitwise or instruction.
-HANDLE_TARGET_OPCODE(G_OR)
-
-/// Generic bitwise exclusive-or instruction.
-HANDLE_TARGET_OPCODE(G_XOR)
-
-
-HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
-
-/// Generic PHI instruction with types.
-HANDLE_TARGET_OPCODE(G_PHI)
-
-/// Generic instruction to materialize the address of an alloca or other
-/// stack-based object.
-HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
-
-/// Generic reference to global value.
-HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE)
-
-/// Generic instruction to extract blocks of bits from the register given
-/// (typically a sub-register COPY after instruction selection).
-HANDLE_TARGET_OPCODE(G_EXTRACT)
-
-HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES)
-
-/// Generic instruction to insert blocks of bits from the registers given into
-/// the source.
-HANDLE_TARGET_OPCODE(G_INSERT)
-
-/// Generic instruction to paste a variable number of components together into a
-/// larger register.
-HANDLE_TARGET_OPCODE(G_MERGE_VALUES)
-
-/// Generic pointer to int conversion.
-HANDLE_TARGET_OPCODE(G_PTRTOINT)
-
-/// Generic int to pointer conversion.
-HANDLE_TARGET_OPCODE(G_INTTOPTR)
-
-/// Generic bitcast. The source and destination types must be different, or a
-/// COPY is the relevant instruction.
-HANDLE_TARGET_OPCODE(G_BITCAST)
-
-/// Generic load.
-HANDLE_TARGET_OPCODE(G_LOAD)
-
-/// Generic store.
-HANDLE_TARGET_OPCODE(G_STORE)
-
-/// Generic conditional branch instruction.
-HANDLE_TARGET_OPCODE(G_BRCOND)
-
-/// Generic indirect branch instruction.
-HANDLE_TARGET_OPCODE(G_BRINDIRECT)
-
-/// Generic intrinsic use (without side effects).
-HANDLE_TARGET_OPCODE(G_INTRINSIC)
-
-/// Generic intrinsic use (with side effects).
-HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS)
-
-/// Generic extension allowing rubbish in high bits.
-HANDLE_TARGET_OPCODE(G_ANYEXT)
-
-/// Generic instruction to discard the high bits of a register. This differs
-/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate
-/// each element individually, G_EXTRACT will typically discard the high
-/// elements of the vector.
-HANDLE_TARGET_OPCODE(G_TRUNC)
-
-/// Generic integer constant.
-HANDLE_TARGET_OPCODE(G_CONSTANT)
-
-/// Generic floating constant.
-HANDLE_TARGET_OPCODE(G_FCONSTANT)
-
-/// Generic va_start instruction. Stores to its one pointer operand.
-HANDLE_TARGET_OPCODE(G_VASTART)
-
-/// Generic va_start instruction. Stores to its one pointer operand.
-HANDLE_TARGET_OPCODE(G_VAARG)
-
-// Generic sign extend
-HANDLE_TARGET_OPCODE(G_SEXT)
-
-// Generic zero extend
-HANDLE_TARGET_OPCODE(G_ZEXT)
-
-// Generic left-shift
-HANDLE_TARGET_OPCODE(G_SHL)
-
-// Generic logical right-shift
-HANDLE_TARGET_OPCODE(G_LSHR)
-
-// Generic arithmetic right-shift
-HANDLE_TARGET_OPCODE(G_ASHR)
-
-/// Generic integer-base comparison, also applicable to vectors of integers.
-HANDLE_TARGET_OPCODE(G_ICMP)
-
-/// Generic floating-point comparison, also applicable to vectors.
-HANDLE_TARGET_OPCODE(G_FCMP)
-
-/// Generic select.
-HANDLE_TARGET_OPCODE(G_SELECT)
-
-/// Generic unsigned add instruction, consuming the normal operands plus a carry
-/// flag, and similarly producing the result and a carry flag.
-HANDLE_TARGET_OPCODE(G_UADDE)
-
-/// Generic unsigned subtract instruction, consuming the normal operands plus a
-/// carry flag, and similarly producing the result and a carry flag.
-HANDLE_TARGET_OPCODE(G_USUBE)
-
-/// Generic signed add instruction, producing the result and a signed overflow
-/// flag.
-HANDLE_TARGET_OPCODE(G_SADDO)
-
-/// Generic signed subtract instruction, producing the result and a signed
-/// overflow flag.
-HANDLE_TARGET_OPCODE(G_SSUBO)
-
-/// Generic unsigned multiply instruction, producing the result and a signed
-/// overflow flag.
-HANDLE_TARGET_OPCODE(G_UMULO)
-
-/// Generic signed multiply instruction, producing the result and a signed
-/// overflow flag.
-HANDLE_TARGET_OPCODE(G_SMULO)
-
-// Multiply two numbers at twice the incoming bit width (unsigned) and return
-// the high half of the result.
-HANDLE_TARGET_OPCODE(G_UMULH)
-
-// Multiply two numbers at twice the incoming bit width (signed) and return
-// the high half of the result.
-HANDLE_TARGET_OPCODE(G_SMULH)
-
-/// Generic FP addition.
-HANDLE_TARGET_OPCODE(G_FADD)
-
-/// Generic FP subtraction.
-HANDLE_TARGET_OPCODE(G_FSUB)
-
-/// Generic FP multiplication.
-HANDLE_TARGET_OPCODE(G_FMUL)
-
-/// Generic FMA multiplication. Behaves like llvm fma intrinsic
-HANDLE_TARGET_OPCODE(G_FMA)
-
-/// Generic FP division.
-HANDLE_TARGET_OPCODE(G_FDIV)
-
-/// Generic FP remainder.
-HANDLE_TARGET_OPCODE(G_FREM)
-
-/// Generic FP exponentiation.
-HANDLE_TARGET_OPCODE(G_FPOW)
-
-/// Generic base-e exponential of a value.
-HANDLE_TARGET_OPCODE(G_FEXP)
-
-/// Generic base-2 exponential of a value.
-HANDLE_TARGET_OPCODE(G_FEXP2)
-
-/// Floating point base-e logarithm of a value.
-HANDLE_TARGET_OPCODE(G_FLOG)
-
-/// Floating point base-2 logarithm of a value.
-HANDLE_TARGET_OPCODE(G_FLOG2)
-
-/// Generic FP negation.
-HANDLE_TARGET_OPCODE(G_FNEG)
-
-/// Generic FP extension.
-HANDLE_TARGET_OPCODE(G_FPEXT)
-
-/// Generic float to signed-int conversion
-HANDLE_TARGET_OPCODE(G_FPTRUNC)
-
-/// Generic float to signed-int conversion
-HANDLE_TARGET_OPCODE(G_FPTOSI)
-
-/// Generic float to unsigned-int conversion
-HANDLE_TARGET_OPCODE(G_FPTOUI)
-
-/// Generic signed-int to float conversion
-HANDLE_TARGET_OPCODE(G_SITOFP)
-
-/// Generic unsigned-int to float conversion
-HANDLE_TARGET_OPCODE(G_UITOFP)
-
-/// Generic pointer offset
-HANDLE_TARGET_OPCODE(G_GEP)
-
-/// Clear the specified number of low bits in a pointer. This rounds the value
-/// *down* to the given alignment.
-HANDLE_TARGET_OPCODE(G_PTR_MASK)
-
-/// Generic BRANCH instruction. This is an unconditional branch.
-HANDLE_TARGET_OPCODE(G_BR)
-
-/// Generic insertelement.
-HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
-
-/// Generic extractelement.
-HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
-
-/// Generic shufflevector.
-HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
-
-/// Generic byte swap.
-HANDLE_TARGET_OPCODE(G_BSWAP)
-
-// TODO: Add more generic opcodes as we move along.
-
-/// Marker for the end of the generic opcode.
-/// This is used to check if an opcode is in the range of the
-/// generic opcodes.
-HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BSWAP)
-
-/// BUILTIN_OP_END - This must be the last enum value in this list.
-/// The target-specific post-isel opcode values start here.
-HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)
Removed: llvm/trunk/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.h (removed)
@@ -1,42 +0,0 @@
-//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target independent instruction opcodes.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETOPCODES_H
-#define LLVM_TARGET_TARGETOPCODES_H
-
-namespace llvm {
-
-/// Invariant opcodes: All instruction sets have these as their low opcodes.
-///
-namespace TargetOpcode {
-enum {
-#define HANDLE_TARGET_OPCODE(OPC) OPC,
-#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
-#include "llvm/Target/TargetOpcodes.def"
-};
-} // end namespace TargetOpcode
-
-/// Check whether the given Opcode is a generic opcode that is not supposed
-/// to appear after ISel.
-inline bool isPreISelGenericOpcode(unsigned Opcode) {
- return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
- Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
-}
-
-/// Check whether the given Opcode is a target-specific opcode.
-inline bool isTargetSpecificOpcode(unsigned Opcode) {
- return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
-}
-} // end namespace llvm
-
-#endif
Removed: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (removed)
@@ -1,1166 +0,0 @@
-//==- Target/TargetRegisterInfo.h - Target Register Information --*- C++ -*-==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes an abstract interface used to get information about a
-// target machines register file. This information is used for a variety of
-// purposed, especially register allocation.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
-#define LLVM_TARGET_TARGETREGISTERINFO_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/iterator_range.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineValueType.h"
-#include "llvm/IR/CallingConv.h"
-#include "llvm/MC/LaneBitmask.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/Printable.h"
-#include <cassert>
-#include <cstdint>
-#include <functional>
-
-namespace llvm {
-
-class BitVector;
-class LiveRegMatrix;
-class MachineFunction;
-class MachineInstr;
-class RegScavenger;
-class VirtRegMap;
-class LiveIntervals;
-
-class TargetRegisterClass {
-public:
- using iterator = const MCPhysReg *;
- using const_iterator = const MCPhysReg *;
- using sc_iterator = const TargetRegisterClass* const *;
-
- // Instance variables filled by tablegen, do not use!
- const MCRegisterClass *MC;
- const uint32_t *SubClassMask;
- const uint16_t *SuperRegIndices;
- const LaneBitmask LaneMask;
- /// Classes with a higher priority value are assigned first by register
- /// allocators using a greedy heuristic. The value is in the range [0,63].
- const uint8_t AllocationPriority;
- /// Whether the class supports two (or more) disjunct subregister indices.
- const bool HasDisjunctSubRegs;
- /// Whether a combination of subregisters can cover every register in the
- /// class. See also the CoveredBySubRegs description in Target.td.
- const bool CoveredBySubRegs;
- const sc_iterator SuperClasses;
- ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
-
- /// Return the register class ID number.
- unsigned getID() const { return MC->getID(); }
-
- /// begin/end - Return all of the registers in this class.
- ///
- iterator begin() const { return MC->begin(); }
- iterator end() const { return MC->end(); }
-
- /// Return the number of registers in this class.
- unsigned getNumRegs() const { return MC->getNumRegs(); }
-
- iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
- getRegisters() const {
- return make_range(MC->begin(), MC->end());
- }
-
- /// Return the specified register in the class.
- unsigned getRegister(unsigned i) const {
- return MC->getRegister(i);
- }
-
- /// Return true if the specified register is included in this register class.
- /// This does not include virtual registers.
- bool contains(unsigned Reg) const {
- return MC->contains(Reg);
- }
-
- /// Return true if both registers are in this class.
- bool contains(unsigned Reg1, unsigned Reg2) const {
- return MC->contains(Reg1, Reg2);
- }
-
- /// Return the cost of copying a value between two registers in this class.
- /// A negative number means the register class is very expensive
- /// to copy e.g. status flag register classes.
- int getCopyCost() const { return MC->getCopyCost(); }
-
- /// Return true if this register class may be used to create virtual
- /// registers.
- bool isAllocatable() const { return MC->isAllocatable(); }
-
- /// Return true if the specified TargetRegisterClass
- /// is a proper sub-class of this TargetRegisterClass.
- bool hasSubClass(const TargetRegisterClass *RC) const {
- return RC != this && hasSubClassEq(RC);
- }
-
- /// Returns true if RC is a sub-class of or equal to this class.
- bool hasSubClassEq(const TargetRegisterClass *RC) const {
- unsigned ID = RC->getID();
- return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
- }
-
- /// Return true if the specified TargetRegisterClass is a
- /// proper super-class of this TargetRegisterClass.
- bool hasSuperClass(const TargetRegisterClass *RC) const {
- return RC->hasSubClass(this);
- }
-
- /// Returns true if RC is a super-class of or equal to this class.
- bool hasSuperClassEq(const TargetRegisterClass *RC) const {
- return RC->hasSubClassEq(this);
- }
-
- /// Returns a bit vector of subclasses, including this one.
- /// The vector is indexed by class IDs.
- ///
- /// To use it, consider the returned array as a chunk of memory that
- /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
- /// contains a bitset of the ID of the subclasses in big-endian style.
-
- /// I.e., the representation of the memory from left to right at the
- /// bit level looks like:
- /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
- /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
- /// Where the number represents the class ID and XXX bits that
- /// should be ignored.
- ///
- /// See the implementation of hasSubClassEq for an example of how it
- /// can be used.
- const uint32_t *getSubClassMask() const {
- return SubClassMask;
- }
-
- /// Returns a 0-terminated list of sub-register indices that project some
- /// super-register class into this register class. The list has an entry for
- /// each Idx such that:
- ///
- /// There exists SuperRC where:
- /// For all Reg in SuperRC:
- /// this->contains(Reg:Idx)
- const uint16_t *getSuperRegIndices() const {
- return SuperRegIndices;
- }
-
- /// Returns a NULL-terminated list of super-classes. The
- /// classes are ordered by ID which is also a topological ordering from large
- /// to small classes. The list does NOT include the current class.
- sc_iterator getSuperClasses() const {
- return SuperClasses;
- }
-
- /// Return true if this TargetRegisterClass is a subset
- /// class of at least one other TargetRegisterClass.
- bool isASubClass() const {
- return SuperClasses[0] != nullptr;
- }
-
- /// Returns the preferred order for allocating registers from this register
- /// class in MF. The raw order comes directly from the .td file and may
- /// include reserved registers that are not allocatable.
- /// Register allocators should also make sure to allocate
- /// callee-saved registers only after all the volatiles are used. The
- /// RegisterClassInfo class provides filtered allocation orders with
- /// callee-saved registers moved to the end.
- ///
- /// The MachineFunction argument can be used to tune the allocatable
- /// registers based on the characteristics of the function, subtarget, or
- /// other criteria.
- ///
- /// By default, this method returns all registers in the class.
- ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
- return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
- }
-
- /// Returns the combination of all lane masks of register in this class.
- /// The lane masks of the registers are the combination of all lane masks
- /// of their subregisters. Returns 1 if there are no subregisters.
- LaneBitmask getLaneMask() const {
- return LaneMask;
- }
-};
-
-/// Extra information, not in MCRegisterDesc, about registers.
-/// These are used by codegen, not by MC.
-struct TargetRegisterInfoDesc {
- unsigned CostPerUse; // Extra cost of instructions using register.
- bool inAllocatableClass; // Register belongs to an allocatable regclass.
-};
-
-/// Each TargetRegisterClass has a per register weight, and weight
-/// limit which must be less than the limits of its pressure sets.
-struct RegClassWeight {
- unsigned RegWeight;
- unsigned WeightLimit;
-};
-
-/// TargetRegisterInfo base class - We assume that the target defines a static
-/// array of TargetRegisterDesc objects that represent all of the machine
-/// registers that the target has. As such, we simply have to track a pointer
-/// to this array so that we can turn register number into a register
-/// descriptor.
-///
-class TargetRegisterInfo : public MCRegisterInfo {
-public:
- using regclass_iterator = const TargetRegisterClass * const *;
- using vt_iterator = const MVT::SimpleValueType *;
- struct RegClassInfo {
- unsigned RegSize, SpillSize, SpillAlignment;
- vt_iterator VTList;
- };
-private:
- const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
- const char *const *SubRegIndexNames; // Names of subreg indexes.
- // Pointer to array of lane masks, one per sub-reg index.
- const LaneBitmask *SubRegIndexLaneMasks;
-
- regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
- LaneBitmask CoveringLanes;
- const RegClassInfo *const RCInfos;
- unsigned HwMode;
-
-protected:
- TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
- regclass_iterator RegClassBegin,
- regclass_iterator RegClassEnd,
- const char *const *SRINames,
- const LaneBitmask *SRILaneMasks,
- LaneBitmask CoveringLanes,
- const RegClassInfo *const RSI,
- unsigned Mode = 0);
- virtual ~TargetRegisterInfo();
-
-public:
- // Register numbers can represent physical registers, virtual registers, and
- // sometimes stack slots. The unsigned values are divided into these ranges:
- //
- // 0 Not a register, can be used as a sentinel.
- // [1;2^30) Physical registers assigned by TableGen.
- // [2^30;2^31) Stack slots. (Rarely used.)
- // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
- //
- // Further sentinels can be allocated from the small negative integers.
- // DenseMapInfo<unsigned> uses -1u and -2u.
-
- /// isStackSlot - Sometimes it is useful the be able to store a non-negative
- /// frame index in a variable that normally holds a register. isStackSlot()
- /// returns true if Reg is in the range used for stack slots.
- ///
- /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
- /// slots, so if a variable may contains a stack slot, always check
- /// isStackSlot() first.
- ///
- static bool isStackSlot(unsigned Reg) {
- return int(Reg) >= (1 << 30);
- }
-
- /// Compute the frame index from a register value representing a stack slot.
- static int stackSlot2Index(unsigned Reg) {
- assert(isStackSlot(Reg) && "Not a stack slot");
- return int(Reg - (1u << 30));
- }
-
- /// Convert a non-negative frame index to a stack slot register value.
- static unsigned index2StackSlot(int FI) {
- assert(FI >= 0 && "Cannot hold a negative frame index.");
- return FI + (1u << 30);
- }
-
- /// Return true if the specified register number is in
- /// the physical register namespace.
- static bool isPhysicalRegister(unsigned Reg) {
- assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
- return int(Reg) > 0;
- }
-
- /// Return true if the specified register number is in
- /// the virtual register namespace.
- static bool isVirtualRegister(unsigned Reg) {
- assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
- return int(Reg) < 0;
- }
-
- /// Convert a virtual register number to a 0-based index.
- /// The first virtual register in a function will get the index 0.
- static unsigned virtReg2Index(unsigned Reg) {
- assert(isVirtualRegister(Reg) && "Not a virtual register");
- return Reg & ~(1u << 31);
- }
-
- /// Convert a 0-based index to a virtual register number.
- /// This is the inverse operation of VirtReg2IndexFunctor below.
- static unsigned index2VirtReg(unsigned Index) {
- return Index | (1u << 31);
- }
-
- /// Return the size in bits of a register from class RC.
- unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).RegSize;
- }
-
- /// Return the size in bytes of the stack slot allocated to hold a spilled
- /// copy of a register from class RC.
- unsigned getSpillSize(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).SpillSize / 8;
- }
-
- /// Return the minimum required alignment in bytes for a spill slot for
- /// a register of this class.
- unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).SpillAlignment / 8;
- }
-
- /// Return true if the given TargetRegisterClass has the ValueType T.
- bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
- for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
- if (MVT(*I) == T)
- return true;
- return false;
- }
-
- /// Loop over all of the value types that can be represented by values
- /// in the given register class.
- vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).VTList;
- }
-
- vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
- vt_iterator I = legalclasstypes_begin(RC);
- while (*I != MVT::Other)
- ++I;
- return I;
- }
-
- /// Returns the Register Class of a physical register of the given type,
- /// picking the most sub register class of the right type that contains this
- /// physreg.
- const TargetRegisterClass *
- getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
-
- /// Return the maximal subclass of the given register class that is
- /// allocatable or NULL.
- const TargetRegisterClass *
- getAllocatableClass(const TargetRegisterClass *RC) const;
-
- /// Returns a bitset indexed by register number indicating if a register is
- /// allocatable or not. If a register class is specified, returns the subset
- /// for the class.
- BitVector getAllocatableSet(const MachineFunction &MF,
- const TargetRegisterClass *RC = nullptr) const;
-
- /// Return the additional cost of using this register instead
- /// of other registers in its class.
- unsigned getCostPerUse(unsigned RegNo) const {
- return InfoDesc[RegNo].CostPerUse;
- }
-
- /// Return true if the register is in the allocation of any register class.
- bool isInAllocatableClass(unsigned RegNo) const {
- return InfoDesc[RegNo].inAllocatableClass;
- }
-
- /// Return the human-readable symbolic target-specific
- /// name for the specified SubRegIndex.
- const char *getSubRegIndexName(unsigned SubIdx) const {
- assert(SubIdx && SubIdx < getNumSubRegIndices() &&
- "This is not a subregister index");
- return SubRegIndexNames[SubIdx-1];
- }
-
- /// Return a bitmask representing the parts of a register that are covered by
- /// SubIdx \see LaneBitmask.
- ///
- /// SubIdx == 0 is allowed, it has the lane mask ~0u.
- LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
- assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
- return SubRegIndexLaneMasks[SubIdx];
- }
-
- /// The lane masks returned by getSubRegIndexLaneMask() above can only be
- /// used to determine if sub-registers overlap - they can't be used to
- /// determine if a set of sub-registers completely cover another
- /// sub-register.
- ///
- /// The X86 general purpose registers have two lanes corresponding to the
- /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
- /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
- /// sub_32bit sub-register.
- ///
- /// On the other hand, the ARM NEON lanes fully cover their registers: The
- /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
- /// This is related to the CoveredBySubRegs property on register definitions.
- ///
- /// This function returns a bit mask of lanes that completely cover their
- /// sub-registers. More precisely, given:
- ///
- /// Covering = getCoveringLanes();
- /// MaskA = getSubRegIndexLaneMask(SubA);
- /// MaskB = getSubRegIndexLaneMask(SubB);
- ///
- /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
- /// SubB.
- LaneBitmask getCoveringLanes() const { return CoveringLanes; }
-
- /// Returns true if the two registers are equal or alias each other.
- /// The registers may be virtual registers.
- bool regsOverlap(unsigned regA, unsigned regB) const {
- if (regA == regB) return true;
- if (isVirtualRegister(regA) || isVirtualRegister(regB))
- return false;
-
- // Regunits are numerically ordered. Find a common unit.
- MCRegUnitIterator RUA(regA, this);
- MCRegUnitIterator RUB(regB, this);
- do {
- if (*RUA == *RUB) return true;
- if (*RUA < *RUB) ++RUA;
- else ++RUB;
- } while (RUA.isValid() && RUB.isValid());
- return false;
- }
-
- /// Returns true if Reg contains RegUnit.
- bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
- for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
- if (*Units == RegUnit)
- return true;
- return false;
- }
-
- /// Return a null-terminated list of all of the callee-saved registers on
- /// this target. The register should be in the order of desired callee-save
- /// stack frame offset. The first register is closest to the incoming stack
- /// pointer if stack grows down, and vice versa.
- /// Notice: This function does not take into account disabled CSRs.
- /// In most cases you will want to use instead the function
- /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
- virtual const MCPhysReg*
- getCalleeSavedRegs(const MachineFunction *MF) const = 0;
-
- /// Return a mask of call-preserved registers for the given calling convention
- /// on the current function. The mask should include all call-preserved
- /// aliases. This is used by the register allocator to determine which
- /// registers can be live across a call.
- ///
- /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
- /// A set bit indicates that all bits of the corresponding register are
- /// preserved across the function call. The bit mask is expected to be
- /// sub-register complete, i.e. if A is preserved, so are all its
- /// sub-registers.
- ///
- /// Bits are numbered from the LSB, so the bit for physical register Reg can
- /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
- ///
- /// A NULL pointer means that no register mask will be used, and call
- /// instructions should use implicit-def operands to indicate call clobbered
- /// registers.
- ///
- virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
- CallingConv::ID) const {
- // The default mask clobbers everything. All targets should override.
- return nullptr;
- }
-
- /// Return a register mask that clobbers everything.
- virtual const uint32_t *getNoPreservedMask() const {
- llvm_unreachable("target does not provide no preserved mask");
- }
-
- /// Return true if all bits that are set in mask \p mask0 are also set in
- /// \p mask1.
- bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
-
- /// Return all the call-preserved register masks defined for this target.
- virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
- virtual ArrayRef<const char *> getRegMaskNames() const = 0;
-
- /// Returns a bitset indexed by physical register number indicating if a
- /// register is a special register that has particular uses and should be
- /// considered unavailable at all times, e.g. stack pointer, return address.
- /// A reserved register:
- /// - is not allocatable
- /// - is considered always live
- /// - is ignored by liveness tracking
- /// It is often necessary to reserve the super registers of a reserved
- /// register as well, to avoid them getting allocated indirectly. You may use
- /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
- virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
-
- /// Returns true if PhysReg is unallocatable and constant throughout the
- /// function. Used by MachineRegisterInfo::isConstantPhysReg().
- virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
-
- /// Physical registers that may be modified within a function but are
- /// guaranteed to be restored before any uses. This is useful for targets that
- /// have call sequences where a GOT register may be updated by the caller
- /// prior to a call and is guaranteed to be restored (also by the caller)
- /// after the call.
- virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
- const MachineFunction &MF) const {
- return false;
- }
-
- /// Prior to adding the live-out mask to a stackmap or patchpoint
- /// instruction, provide the target the opportunity to adjust it (mainly to
- /// remove pseudo-registers that should be ignored).
- virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
-
- /// Return a super-register of the specified register
- /// Reg so its sub-register of index SubIdx is Reg.
- unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
- const TargetRegisterClass *RC) const {
- return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
- }
-
- /// Return a subclass of the specified register
- /// class A so that each register in it has a sub-register of the
- /// specified sub-register index which is in the specified register class B.
- ///
- /// TableGen will synthesize missing A sub-classes.
- virtual const TargetRegisterClass *
- getMatchingSuperRegClass(const TargetRegisterClass *A,
- const TargetRegisterClass *B, unsigned Idx) const;
-
- // For a copy-like instruction that defines a register of class DefRC with
- // subreg index DefSubReg, reading from another source with class SrcRC and
- // subregister SrcSubReg return true if this is a preferable copy
- // instruction or an earlier use should be used.
- virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
- unsigned DefSubReg,
- const TargetRegisterClass *SrcRC,
- unsigned SrcSubReg) const;
-
- /// Returns the largest legal sub-class of RC that
- /// supports the sub-register index Idx.
- /// If no such sub-class exists, return NULL.
- /// If all registers in RC already have an Idx sub-register, return RC.
- ///
- /// TableGen generates a version of this function that is good enough in most
- /// cases. Targets can override if they have constraints that TableGen
- /// doesn't understand. For example, the x86 sub_8bit sub-register index is
- /// supported by the full GR32 register class in 64-bit mode, but only by the
- /// GR32_ABCD regiister class in 32-bit mode.
- ///
- /// TableGen will synthesize missing RC sub-classes.
- virtual const TargetRegisterClass *
- getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
- assert(Idx == 0 && "Target has no sub-registers");
- return RC;
- }
-
- /// Return the subregister index you get from composing
- /// two subregister indices.
- ///
- /// The special null sub-register index composes as the identity.
- ///
- /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
- /// returns c. Note that composeSubRegIndices does not tell you about illegal
- /// compositions. If R does not have a subreg a, or R:a does not have a subreg
- /// b, composeSubRegIndices doesn't tell you.
- ///
- /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
- /// ssub_0:S0 - ssub_3:S3 subregs.
- /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
- unsigned composeSubRegIndices(unsigned a, unsigned b) const {
- if (!a) return b;
- if (!b) return a;
- return composeSubRegIndicesImpl(a, b);
- }
-
- /// Transforms a LaneMask computed for one subregister to the lanemask that
- /// would have been computed when composing the subsubregisters with IdxA
- /// first. @sa composeSubRegIndices()
- LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
- LaneBitmask Mask) const {
- if (!IdxA)
- return Mask;
- return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
- }
-
- /// Transform a lanemask given for a virtual register to the corresponding
- /// lanemask before using subregister with index \p IdxA.
- /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
- /// valie lane mask (no invalid bits set) the following holds:
- /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
- /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
- /// => X1 == Mask
- LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
- LaneBitmask LaneMask) const {
- if (!IdxA)
- return LaneMask;
- return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
- }
-
- /// Debugging helper: dump register in human readable form to dbgs() stream.
- static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
- const TargetRegisterInfo* TRI = nullptr);
-
-protected:
- /// Overridden by TableGen in targets that have sub-registers.
- virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
- llvm_unreachable("Target has no sub-registers");
- }
-
- /// Overridden by TableGen in targets that have sub-registers.
- virtual LaneBitmask
- composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
- llvm_unreachable("Target has no sub-registers");
- }
-
- virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
- LaneBitmask) const {
- llvm_unreachable("Target has no sub-registers");
- }
-
-public:
- /// Find a common super-register class if it exists.
- ///
- /// Find a register class, SuperRC and two sub-register indices, PreA and
- /// PreB, such that:
- ///
- /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
- ///
- /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
- ///
- /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
- ///
- /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
- /// requirements, and there is no register class with a smaller spill size
- /// that satisfies the requirements.
- ///
- /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
- ///
- /// Either of the PreA and PreB sub-register indices may be returned as 0. In
- /// that case, the returned register class will be a sub-class of the
- /// corresponding argument register class.
- ///
- /// The function returns NULL if no register class can be found.
- const TargetRegisterClass*
- getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
- const TargetRegisterClass *RCB, unsigned SubB,
- unsigned &PreA, unsigned &PreB) const;
-
- //===--------------------------------------------------------------------===//
- // Register Class Information
- //
-protected:
- const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
- return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
- }
-
-public:
- /// Register class iterators
- regclass_iterator regclass_begin() const { return RegClassBegin; }
- regclass_iterator regclass_end() const { return RegClassEnd; }
- iterator_range<regclass_iterator> regclasses() const {
- return make_range(regclass_begin(), regclass_end());
- }
-
- unsigned getNumRegClasses() const {
- return (unsigned)(regclass_end()-regclass_begin());
- }
-
- /// Returns the register class associated with the enumeration value.
- /// See class MCOperandInfo.
- const TargetRegisterClass *getRegClass(unsigned i) const {
- assert(i < getNumRegClasses() && "Register Class ID out of range");
- return RegClassBegin[i];
- }
-
- /// Returns the name of the register class.
- const char *getRegClassName(const TargetRegisterClass *Class) const {
- return MCRegisterInfo::getRegClassName(Class->MC);
- }
-
- /// Find the largest common subclass of A and B.
- /// Return NULL if there is no common subclass.
- /// The common subclass should contain
- /// simple value type SVT if it is not the Any type.
- const TargetRegisterClass *
- getCommonSubClass(const TargetRegisterClass *A,
- const TargetRegisterClass *B,
- const MVT::SimpleValueType SVT =
- MVT::SimpleValueType::Any) const;
-
- /// Returns a TargetRegisterClass used for pointer values.
- /// If a target supports multiple different pointer register classes,
- /// kind specifies which one is indicated.
- virtual const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
- llvm_unreachable("Target didn't implement getPointerRegClass!");
- }
-
- /// Returns a legal register class to copy a register in the specified class
- /// to or from. If it is possible to copy the register directly without using
- /// a cross register class copy, return the specified RC. Returns NULL if it
- /// is not possible to copy between two registers of the specified class.
- virtual const TargetRegisterClass *
- getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- return RC;
- }
-
- /// Returns the largest super class of RC that is legal to use in the current
- /// sub-target and has the same spill size.
- /// The returned register class can be used to create virtual registers which
- /// means that all its registers can be copied and spilled.
- virtual const TargetRegisterClass *
- getLargestLegalSuperClass(const TargetRegisterClass *RC,
- const MachineFunction &) const {
- /// The default implementation is very conservative and doesn't allow the
- /// register allocator to inflate register classes.
- return RC;
- }
-
- /// Return the register pressure "high water mark" for the specific register
- /// class. The scheduler is in high register pressure mode (for the specific
- /// register class) if it goes over the limit.
- ///
- /// Note: this is the old register pressure model that relies on a manually
- /// specified representative register class per value type.
- virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const {
- return 0;
- }
-
- /// Return a heuristic for the machine scheduler to compare the profitability
- /// of increasing one register pressure set versus another. The scheduler
- /// will prefer increasing the register pressure of the set which returns
- /// the largest value for this function.
- virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
- unsigned PSetID) const {
- return PSetID;
- }
-
- /// Get the weight in units of pressure for this register class.
- virtual const RegClassWeight &getRegClassWeight(
- const TargetRegisterClass *RC) const = 0;
-
- /// Get the weight in units of pressure for this register unit.
- virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
-
- /// Get the number of dimensions of register pressure.
- virtual unsigned getNumRegPressureSets() const = 0;
-
- /// Get the name of this register unit pressure set.
- virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
-
- /// Get the register unit pressure limit for this dimension.
- /// This limit must be adjusted dynamically for reserved registers.
- virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
- unsigned Idx) const = 0;
-
- /// Get the dimensions of register pressure impacted by this register class.
- /// Returns a -1 terminated array of pressure set IDs.
- virtual const int *getRegClassPressureSets(
- const TargetRegisterClass *RC) const = 0;
-
- /// Get the dimensions of register pressure impacted by this register unit.
- /// Returns a -1 terminated array of pressure set IDs.
- virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
-
- /// Get a list of 'hint' registers that the register allocator should try
- /// first when allocating a physical register for the virtual register
- /// VirtReg. These registers are effectively moved to the front of the
- /// allocation order. If true is returned, regalloc will try to only use
- /// hints to the greatest extent possible even if it means spilling.
- ///
- /// The Order argument is the allocation order for VirtReg's register class
- /// as returned from RegisterClassInfo::getOrder(). The hint registers must
- /// come from Order, and they must not be reserved.
- ///
- /// The default implementation of this function can resolve
- /// target-independent hints provided to MRI::setRegAllocationHint with
- /// HintType == 0. Targets that override this function should defer to the
- /// default implementation if they have no reason to change the allocation
- /// order for VirtReg. There may be target-independent hints.
- virtual bool getRegAllocationHints(unsigned VirtReg,
- ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
- const MachineFunction &MF,
- const VirtRegMap *VRM = nullptr,
- const LiveRegMatrix *Matrix = nullptr)
- const;
-
- /// A callback to allow target a chance to update register allocation hints
- /// when a register is "changed" (e.g. coalesced) to another register.
- /// e.g. On ARM, some virtual registers should target register pairs,
- /// if one of pair is coalesced to another register, the allocation hint of
- /// the other half of the pair should be changed to point to the new register.
- virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
- MachineFunction &MF) const {
- // Do nothing.
- }
-
- /// Allow the target to reverse allocation order of local live ranges. This
- /// will generally allocate shorter local live ranges first. For targets with
- /// many registers, this could reduce regalloc compile time by a large
- /// factor. It is disabled by default for three reasons:
- /// (1) Top-down allocation is simpler and easier to debug for targets that
- /// don't benefit from reversing the order.
- /// (2) Bottom-up allocation could result in poor evicition decisions on some
- /// targets affecting the performance of compiled code.
- /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
- virtual bool reverseLocalAssignment() const { return false; }
-
- /// Allow the target to override the cost of using a callee-saved register for
- /// the first time. Default value of 0 means we will use a callee-saved
- /// register if it is available.
- virtual unsigned getCSRFirstUseCost() const { return 0; }
-
- /// Returns true if the target requires (and can make use of) the register
- /// scavenger.
- virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
- return false;
- }
-
- /// Returns true if the target wants to use frame pointer based accesses to
- /// spill to the scavenger emergency spill slot.
- virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
- return true;
- }
-
- /// Returns true if the target requires post PEI scavenging of registers for
- /// materializing frame index constants.
- virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
- return false;
- }
-
- /// Returns true if the target requires using the RegScavenger directly for
- /// frame elimination despite using requiresFrameIndexScavenging.
- virtual bool requiresFrameIndexReplacementScavenging(
- const MachineFunction &MF) const {
- return false;
- }
-
- /// Returns true if the target wants the LocalStackAllocation pass to be run
- /// and virtual base registers used for more efficient stack access.
- virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
- return false;
- }
-
- /// Return true if target has reserved a spill slot in the stack frame of
- /// the given function for the specified register. e.g. On x86, if the frame
- /// register is required, the first fixed stack object is reserved as its
- /// spill slot. This tells PEI not to create a new stack frame
- /// object for the given register. It should be called only after
- /// determineCalleeSaves().
- virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
- int &FrameIdx) const {
- return false;
- }
-
- /// Returns true if the live-ins should be tracked after register allocation.
- virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
- return false;
- }
-
- /// True if the stack can be realigned for the target.
- virtual bool canRealignStack(const MachineFunction &MF) const;
-
- /// True if storage within the function requires the stack pointer to be
- /// aligned more than the normal calling convention calls for.
- /// This cannot be overriden by the target, but canRealignStack can be
- /// overridden.
- bool needsStackRealignment(const MachineFunction &MF) const;
-
- /// Get the offset from the referenced frame index in the instruction,
- /// if there is one.
- virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
- int Idx) const {
- return 0;
- }
-
- /// Returns true if the instruction's frame index reference would be better
- /// served by a base register other than FP or SP.
- /// Used by LocalStackFrameAllocation to determine which frame index
- /// references it should create new base registers for.
- virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
- return false;
- }
-
- /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
- /// before insertion point I.
- virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
- unsigned BaseReg, int FrameIdx,
- int64_t Offset) const {
- llvm_unreachable("materializeFrameBaseRegister does not exist on this "
- "target");
- }
-
- /// Resolve a frame index operand of an instruction
- /// to reference the indicated base register plus offset instead.
- virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
- int64_t Offset) const {
- llvm_unreachable("resolveFrameIndex does not exist on this target");
- }
-
- /// Determine whether a given base register plus offset immediate is
- /// encodable to resolve a frame index.
- virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
- int64_t Offset) const {
- llvm_unreachable("isFrameOffsetLegal does not exist on this target");
- }
-
- /// Spill the register so it can be used by the register scavenger.
- /// Return true if the register was spilled, false otherwise.
- /// If this function does not spill the register, the scavenger
- /// will instead spill it to the emergency spill slot.
- virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator &UseMI,
- const TargetRegisterClass *RC,
- unsigned Reg) const {
- return false;
- }
-
- /// This method must be overriden to eliminate abstract frame indices from
- /// instructions which may use them. The instruction referenced by the
- /// iterator contains an MO_FrameIndex operand which must be eliminated by
- /// this method. This method may modify or replace the specified instruction,
- /// as long as it keeps the iterator pointing at the finished product.
- /// SPAdj is the SP adjustment due to call frame setup instruction.
- /// FIOperandNum is the FI operand number.
- virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
- int SPAdj, unsigned FIOperandNum,
- RegScavenger *RS = nullptr) const = 0;
-
- /// Return the assembly name for \p Reg.
- virtual StringRef getRegAsmName(unsigned Reg) const {
- // FIXME: We are assuming that the assembly name is equal to the TableGen
- // name converted to lower case
- //
- // The TableGen name is the name of the definition for this register in the
- // target's tablegen files. For example, the TableGen name of
- // def EAX : Register <...>; is "EAX"
- return StringRef(getName(Reg));
- }
-
- //===--------------------------------------------------------------------===//
- /// Subtarget Hooks
-
- /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
- virtual bool shouldCoalesce(MachineInstr *MI,
- const TargetRegisterClass *SrcRC,
- unsigned SubReg,
- const TargetRegisterClass *DstRC,
- unsigned DstSubReg,
- const TargetRegisterClass *NewRC,
- LiveIntervals &LIS) const
- { return true; }
-
- //===--------------------------------------------------------------------===//
- /// Debug information queries.
-
- /// getFrameRegister - This method should return the register used as a base
- /// for values allocated in the current stack frame.
- virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
-
- /// Mark a register and all its aliases as reserved in the given set.
- void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
-
- /// Returns true if for every register in the set all super registers are part
- /// of the set as well.
- bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
- ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
-};
-
-//===----------------------------------------------------------------------===//
-// SuperRegClassIterator
-//===----------------------------------------------------------------------===//
-//
-// Iterate over the possible super-registers for a given register class. The
-// iterator will visit a list of pairs (Idx, Mask) corresponding to the
-// possible classes of super-registers.
-//
-// Each bit mask will have at least one set bit, and each set bit in Mask
-// corresponds to a SuperRC such that:
-//
-// For all Reg in SuperRC: Reg:Idx is in RC.
-//
-// The iterator can include (O, RC->getSubClassMask()) as the first entry which
-// also satisfies the above requirement, assuming Reg:0 == Reg.
-//
-class SuperRegClassIterator {
- const unsigned RCMaskWords;
- unsigned SubReg = 0;
- const uint16_t *Idx;
- const uint32_t *Mask;
-
-public:
- /// Create a SuperRegClassIterator that visits all the super-register classes
- /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
- SuperRegClassIterator(const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- bool IncludeSelf = false)
- : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
- Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
- if (!IncludeSelf)
- ++*this;
- }
-
- /// Returns true if this iterator is still pointing at a valid entry.
- bool isValid() const { return Idx; }
-
- /// Returns the current sub-register index.
- unsigned getSubReg() const { return SubReg; }
-
- /// Returns the bit mask of register classes that getSubReg() projects into
- /// RC.
- /// See TargetRegisterClass::getSubClassMask() for how to use it.
- const uint32_t *getMask() const { return Mask; }
-
- /// Advance iterator to the next entry.
- void operator++() {
- assert(isValid() && "Cannot move iterator past end.");
- Mask += RCMaskWords;
- SubReg = *Idx++;
- if (!SubReg)
- Idx = nullptr;
- }
-};
-
-//===----------------------------------------------------------------------===//
-// BitMaskClassIterator
-//===----------------------------------------------------------------------===//
-/// This class encapuslates the logic to iterate over bitmask returned by
-/// the various RegClass related APIs.
-/// E.g., this class can be used to iterate over the subclasses provided by
-/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
-class BitMaskClassIterator {
- /// Total number of register classes.
- const unsigned NumRegClasses;
- /// Base index of CurrentChunk.
- /// In other words, the number of bit we read to get at the
- /// beginning of that chunck.
- unsigned Base = 0;
- /// Adjust base index of CurrentChunk.
- /// Base index + how many bit we read within CurrentChunk.
- unsigned Idx = 0;
- /// Current register class ID.
- unsigned ID = 0;
- /// Mask we are iterating over.
- const uint32_t *Mask;
- /// Current chunk of the Mask we are traversing.
- uint32_t CurrentChunk;
-
- /// Move ID to the next set bit.
- void moveToNextID() {
- // If the current chunk of memory is empty, move to the next one,
- // while making sure we do not go pass the number of register
- // classes.
- while (!CurrentChunk) {
- // Move to the next chunk.
- Base += 32;
- if (Base >= NumRegClasses) {
- ID = NumRegClasses;
- return;
- }
- CurrentChunk = *++Mask;
- Idx = Base;
- }
- // Otherwise look for the first bit set from the right
- // (representation of the class ID is big endian).
- // See getSubClassMask for more details on the representation.
- unsigned Offset = countTrailingZeros(CurrentChunk);
- // Add the Offset to the adjusted base number of this chunk: Idx.
- // This is the ID of the register class.
- ID = Idx + Offset;
-
- // Consume the zeros, if any, and the bit we just read
- // so that we are at the right spot for the next call.
- // Do not do Offset + 1 because Offset may be 31 and 32
- // will be UB for the shift, though in that case we could
- // have make the chunk being equal to 0, but that would
- // have introduced a if statement.
- moveNBits(Offset);
- moveNBits(1);
- }
-
- /// Move \p NumBits Bits forward in CurrentChunk.
- void moveNBits(unsigned NumBits) {
- assert(NumBits < 32 && "Undefined behavior spotted!");
- // Consume the bit we read for the next call.
- CurrentChunk >>= NumBits;
- // Adjust the base for the chunk.
- Idx += NumBits;
- }
-
-public:
- /// Create a BitMaskClassIterator that visits all the register classes
- /// represented by \p Mask.
- ///
- /// \pre \p Mask != nullptr
- BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
- : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
- // Move to the first ID.
- moveToNextID();
- }
-
- /// Returns true if this iterator is still pointing at a valid entry.
- bool isValid() const { return getID() != NumRegClasses; }
-
- /// Returns the current register class ID.
- unsigned getID() const { return ID; }
-
- /// Advance iterator to the next entry.
- void operator++() {
- assert(isValid() && "Cannot move iterator past end.");
- moveToNextID();
- }
-};
-
-// This is useful when building IndexedMaps keyed on virtual registers
-struct VirtReg2IndexFunctor {
- using argument_type = unsigned;
- unsigned operator()(unsigned Reg) const {
- return TargetRegisterInfo::virtReg2Index(Reg);
- }
-};
-
-/// Prints virtual and physical registers with or without a TRI instance.
-///
-/// The format is:
-/// %noreg - NoRegister
-/// %vreg5 - a virtual register.
-/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
-/// %EAX - a physical register
-/// %physreg17 - a physical register when no TRI instance given.
-///
-/// Usage: OS << PrintReg(Reg, TRI) << '\n';
-Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
- unsigned SubRegIdx = 0);
-
-/// Create Printable object to print register units on a \ref raw_ostream.
-///
-/// Register units are named after their root registers:
-///
-/// AL - Single root.
-/// FP0~ST7 - Dual roots.
-///
-/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
-Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
-
-/// \brief Create Printable object to print virtual registers and physical
-/// registers on a \ref raw_ostream.
-Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
-
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETREGISTERINFO_H
Removed: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=318489&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (removed)
@@ -1,255 +0,0 @@
-//===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the subtarget options of a Target machine.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
-#define LLVM_TARGET_TARGETSUBTARGETINFO_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/PBQPRAConstraint.h"
-#include "llvm/CodeGen/ScheduleDAGMutation.h"
-#include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/CodeGen.h"
-#include <memory>
-#include <vector>
-
-
-namespace llvm {
-
-class CallLowering;
-class InstrItineraryData;
-struct InstrStage;
-class InstructionSelector;
-class LegalizerInfo;
-class MachineInstr;
-struct MachineSchedPolicy;
-struct MCReadAdvanceEntry;
-struct MCWriteLatencyEntry;
-struct MCWriteProcResEntry;
-class RegisterBankInfo;
-class SDep;
-class SelectionDAGTargetInfo;
-struct SubtargetFeatureKV;
-struct SubtargetInfoKV;
-class SUnit;
-class TargetFrameLowering;
-class TargetInstrInfo;
-class TargetLowering;
-class TargetRegisterClass;
-class TargetRegisterInfo;
-class TargetSchedModel;
-class Triple;
-
-//===----------------------------------------------------------------------===//
-///
-/// TargetSubtargetInfo - Generic base class for all target subtargets. All
-/// Target-specific options that control code generation and printing should
-/// be exposed through a TargetSubtargetInfo-derived class.
-///
-class TargetSubtargetInfo : public MCSubtargetInfo {
-protected: // Can only create subclasses...
- TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
- ArrayRef<SubtargetFeatureKV> PF,
- ArrayRef<SubtargetFeatureKV> PD,
- const SubtargetInfoKV *ProcSched,
- const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL,
- const MCReadAdvanceEntry *RA, const InstrStage *IS,
- const unsigned *OC, const unsigned *FP);
-
-public:
- // AntiDepBreakMode - Type of anti-dependence breaking that should
- // be performed before post-RA scheduling.
- using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
- using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
-
- TargetSubtargetInfo() = delete;
- TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
- TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
- ~TargetSubtargetInfo() override;
-
- virtual bool isXRaySupported() const { return false; }
-
- // Interfaces to the major aspects of target machine information:
- //
- // -- Instruction opcode and operand information
- // -- Pipelines and scheduling information
- // -- Stack frame information
- // -- Selection DAG lowering information
- // -- Call lowering information
- //
- // N.B. These objects may change during compilation. It's not safe to cache
- // them between functions.
- virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
- virtual const TargetFrameLowering *getFrameLowering() const {
- return nullptr;
- }
- virtual const TargetLowering *getTargetLowering() const { return nullptr; }
- virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
- return nullptr;
- }
- virtual const CallLowering *getCallLowering() const { return nullptr; }
-
- // FIXME: This lets targets specialize the selector by subtarget (which lets
- // us do things like a dedicated avx512 selector). However, we might want
- // to also specialize selectors by MachineFunction, which would let us be
- // aware of optsize/optnone and such.
- virtual const InstructionSelector *getInstructionSelector() const {
- return nullptr;
- }
-
- virtual unsigned getHwMode() const { return 0; }
-
- /// Target can subclass this hook to select a different DAG scheduler.
- virtual RegisterScheduler::FunctionPassCtor
- getDAGScheduler(CodeGenOpt::Level) const {
- return nullptr;
- }
-
- virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
-
- /// getRegisterInfo - If register information is available, return it. If
- /// not, return null.
- virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
-
- /// If the information for the register banks is available, return it.
- /// Otherwise return nullptr.
- virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
-
- /// getInstrItineraryData - Returns instruction itinerary data for the target
- /// or specific subtarget.
- virtual const InstrItineraryData *getInstrItineraryData() const {
- return nullptr;
- }
-
- /// Resolve a SchedClass at runtime, where SchedClass identifies an
- /// MCSchedClassDesc with the isVariant property. This may return the ID of
- /// another variant SchedClass, but repeated invocation must quickly terminate
- /// in a nonvariant SchedClass.
- virtual unsigned resolveSchedClass(unsigned SchedClass,
- const MachineInstr *MI,
- const TargetSchedModel *SchedModel) const {
- return 0;
- }
-
- /// \brief True if the subtarget should run MachineScheduler after aggressive
- /// coalescing.
- ///
- /// This currently replaces the SelectionDAG scheduler with the "source" order
- /// scheduler (though see below for an option to turn this off and use the
- /// TargetLowering preference). It does not yet disable the postRA scheduler.
- virtual bool enableMachineScheduler() const;
-
- /// \brief Support printing of [latency:throughput] comment in output .S file.
- virtual bool supportPrintSchedInfo() const { return false; }
-
- /// \brief True if the machine scheduler should disable the TLI preference
- /// for preRA scheduling with the source level scheduler.
- virtual bool enableMachineSchedDefaultSched() const { return true; }
-
- /// \brief True if the subtarget should enable joining global copies.
- ///
- /// By default this is enabled if the machine scheduler is enabled, but
- /// can be overridden.
- virtual bool enableJoinGlobalCopies() const;
-
- /// True if the subtarget should run a scheduler after register allocation.
- ///
- /// By default this queries the PostRAScheduling bit in the scheduling model
- /// which is the preferred way to influence this.
- virtual bool enablePostRAScheduler() const;
-
- /// \brief True if the subtarget should run the atomic expansion pass.
- virtual bool enableAtomicExpand() const;
-
- /// \brief Override generic scheduling policy within a region.
- ///
- /// This is a convenient way for targets that don't provide any custom
- /// scheduling heuristics (no custom MachineSchedStrategy) to make
- /// changes to the generic scheduling policy.
- virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {}
-
- // \brief Perform target specific adjustments to the latency of a schedule
- // dependency.
- virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
-
- // For use with PostRAScheduling: get the anti-dependence breaking that should
- // be performed before post-RA scheduling.
- virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
-
- // For use with PostRAScheduling: in CriticalPathRCs, return any register
- // classes that should only be considered for anti-dependence breaking if they
- // are on the critical path.
- virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
- return CriticalPathRCs.clear();
- }
-
- // \brief Provide an ordered list of schedule DAG mutations for the post-RA
- // scheduler.
- virtual void getPostRAMutations(
- std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
- }
-
- // \brief Provide an ordered list of schedule DAG mutations for the machine
- // pipeliner.
- virtual void getSMSMutations(
- std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
- }
-
- // For use with PostRAScheduling: get the minimum optimization level needed
- // to enable post-RA scheduling.
- virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
- return CodeGenOpt::Default;
- }
-
- /// \brief True if the subtarget should run the local reassignment
- /// heuristic of the register allocator.
- /// This heuristic may be compile time intensive, \p OptLevel provides
- /// a finer grain to tune the register allocator.
- virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
-
- /// \brief True if the subtarget should consider the cost of local intervals
- /// created by a split candidate when choosing the best split candidate. This
- /// heuristic may be compile time intensive.
- virtual bool enableAdvancedRASplitCost() const;
-
- /// \brief Enable use of alias analysis during code generation (during MI
- /// scheduling, DAGCombine, etc.).
- virtual bool useAA() const;
-
- /// \brief Enable the use of the early if conversion pass.
- virtual bool enableEarlyIfConversion() const { return false; }
-
- /// \brief Return PBQPConstraint(s) for the target.
- ///
- /// Override to provide custom PBQP constraints.
- virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
- return nullptr;
- }
-
- /// Enable tracking of subregister liveness in register allocator.
- /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
- /// possible.
- virtual bool enableSubRegLiveness() const { return false; }
-
- /// Returns string representation of scheduler comment
- std::string getSchedInfoStr(const MachineInstr &MI) const override;
- std::string getSchedInfoStr(MCInst const &MCI) const override;
-};
-
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
Modified: llvm/trunk/include/llvm/module.modulemap
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/module.modulemap?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/include/llvm/module.modulemap (original)
+++ llvm/trunk/include/llvm/module.modulemap Thu Nov 16 17:07:10 2017
@@ -27,14 +27,12 @@ module LLVM_Backend {
// These are intended for (repeated) textual inclusion.
textual header "CodeGen/DIEValue.def"
textual header "CodeGen/RuntimeLibcalls.def"
+ textual header "CodeGen/TargetOpcodes.def"
}
module Target {
umbrella "Target"
module * { export * }
-
- // This is intended for (repeated) textual inclusion.
- textual header "Target/TargetOpcodes.def"
}
}
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Nov 16 17:07:10 2017
@@ -29,13 +29,13 @@
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <map>
#include <set>
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Nov 16 17:07:10 2017
@@ -19,8 +19,8 @@
#include "AntiDepBreaker.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Compiler.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
#include <set>
#include <vector>
Modified: llvm/trunk/lib/CodeGen/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Analysis.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Analysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/Analysis.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
@@ -25,8 +27,6 @@
#include "llvm/IR/Module.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/GlobalStatus.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,8 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Mangler.h"
#include "llvm/IR/Module.h"
@@ -29,9 +31,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/FormattedStream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
ARMException::ARMException(AsmPrinter *A) : DwarfCFIExceptionBase(A) {}
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AddressPool.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AddressPool.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AddressPool.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AddressPool.cpp Thu Nov 16 17:07:10 2017
@@ -10,9 +10,9 @@
#include "AddressPool.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCStreamer.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include <utility>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -53,6 +53,11 @@
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Comdat.h"
#include "llvm/IR/Constant.h"
@@ -102,13 +107,8 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cinttypes>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,8 @@
#include "llvm/CodeGen/DIE.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -28,9 +30,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Nov 16 17:07:10 2017
@@ -18,6 +18,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
@@ -34,8 +36,6 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp Thu Nov 16 17:07:10 2017
@@ -20,9 +20,9 @@
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/TinyPtrVector.h"
#include "llvm/ADT/Triple.h"
@@ -35,6 +35,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/DebugInfo/CodeView/CVTypeVisitor.h"
#include "llvm/DebugInfo/CodeView/CodeView.h"
@@ -66,13 +70,9 @@
#include "llvm/Support/Endian.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/ScopedPrinter.h"
#include "llvm/Support/SMLoc.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
+#include "llvm/Support/ScopedPrinter.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cctype>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp Thu Nov 16 17:07:10 2017
@@ -15,14 +15,14 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <map>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp Thu Nov 16 17:07:10 2017
@@ -19,9 +19,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/MC/MCStreamer.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,9 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Mangler.h"
#include "llvm/IR/Module.h"
@@ -31,11 +34,8 @@
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
DwarfCFIExceptionBase::DwarfCFIExceptionBase(AsmPrinter *A)
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Nov 16 17:07:10 2017
@@ -27,21 +27,21 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/GlobalVariable.h"
-#include "llvm/MC/MachineLocation.h"
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/Casting.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Nov 16 17:07:10 2017
@@ -39,6 +39,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -63,11 +66,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp Thu Nov 16 17:07:10 2017
@@ -15,9 +15,9 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp Thu Nov 16 17:07:10 2017
@@ -22,6 +22,9 @@
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/GlobalValue.h"
@@ -33,9 +36,6 @@
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <string>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/EHStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/EHStreamer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/EHStreamer.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/EHStreamer.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -29,7 +30,6 @@
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/LEB128.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/GCMetadataPrinter.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/GCs.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
@@ -26,7 +27,6 @@
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -11,13 +11,14 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/GCMetadataPrinter.h"
#include "llvm/CodeGen/GCs.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Mangler.h"
@@ -26,7 +27,6 @@
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include <cctype>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,11 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Mangler.h"
@@ -33,12 +38,7 @@
#include "llvm/MC/MCWin64EH.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
WinException::WinException(AsmPrinter *A) : EHStreamer(A) {
Modified: llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/AtomicExpandPass.cpp Thu Nov 16 17:07:10 2017
@@ -20,7 +20,9 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/AtomicExpandUtils.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
@@ -43,9 +45,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/BasicTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BasicTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BasicTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/BasicTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Thu Nov 16 17:07:10 2017
@@ -40,7 +40,10 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -54,9 +57,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstddef>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/BranchRelaxation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchRelaxation.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchRelaxation.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchRelaxation.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,8 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
@@ -23,8 +25,6 @@
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Thu Nov 16 17:07:10 2017
@@ -17,11 +17,11 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <tuple>
Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original)
+++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Thu Nov 16 17:07:10 2017
@@ -15,14 +15,14 @@
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp Thu Nov 16 17:07:10 2017
@@ -36,7 +36,9 @@
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -80,10 +82,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/BypassSlowDivision.h"
#include "llvm/Transforms/Utils/Cloning.h"
Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Nov 16 17:07:10 2017
@@ -27,12 +27,12 @@
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <map>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Thu Nov 16 17:07:10 2017
@@ -30,12 +30,12 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)
+++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Thu Nov 16 17:07:10 2017
@@ -35,13 +35,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/PassRegistry.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Thu Nov 16 17:07:10 2017
@@ -19,7 +19,9 @@
#include "llvm/Analysis/EHPersonalities.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
@@ -30,9 +32,7 @@
#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/Local.h"
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp Thu Nov 16 17:07:10 2017
@@ -31,11 +31,11 @@
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "expand-isel-pseudos"
Modified: llvm/trunk/lib/CodeGen/ExpandMemCmp.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandMemCmp.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandMemCmp.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandMemCmp.cpp Thu Nov 16 17:07:10 2017
@@ -18,10 +18,10 @@
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/IRBuilder.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
Modified: llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp Thu Nov 16 17:07:10 2017
@@ -18,10 +18,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/FEntryInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/FEntryInserter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/FEntryInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/FEntryInserter.cpp Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GCRootLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCRootLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GCRootLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCRootLowering.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,8 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
@@ -27,8 +29,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Module.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Nov 16 17:07:10 2017
@@ -26,7 +26,11 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
@@ -54,12 +58,8 @@
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp Thu Nov 16 17:07:10 2017
@@ -19,15 +19,15 @@
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Config/config.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define DEBUG_TYPE "instruction-select"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp Thu Nov 16 17:07:10 2017
@@ -19,10 +19,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#define DEBUG_TYPE "instructionselector"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp Thu Nov 16 17:07:10 2017
@@ -16,16 +16,16 @@
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
+#include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Nov 16 17:07:10 2017
@@ -17,10 +17,10 @@
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <sstream>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp Thu Nov 16 17:07:10 2017
@@ -22,11 +22,11 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetOpcodes.h"
#include <algorithm>
#include <map>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Thu Nov 16 17:07:10 2017
@@ -16,9 +16,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfo.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp Thu Nov 16 17:07:10 2017
@@ -26,9 +26,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/IR/Function.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
+#include "llvm/IR/Function.h"
#include "llvm/Pass.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/CommandLine.h"
@@ -36,9 +39,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp Thu Nov 16 17:07:10 2017
@@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define DEBUG_TYPE "registerbank"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Thu Nov 16 17:07:10 2017
@@ -20,12 +20,12 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm> // For std::max.
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp Thu Nov 16 17:07:10 2017
@@ -19,8 +19,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#define DEBUG_TYPE "globalisel-utils"
Modified: llvm/trunk/lib/CodeGen/GlobalMerge.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalMerge.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalMerge.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalMerge.cpp Thu Nov 16 17:07:10 2017
@@ -70,6 +70,7 @@
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
@@ -88,12 +89,11 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
-#include <cstdint>
#include <cstddef>
+#include <cstdint>
#include <string>
#include <vector>
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Thu Nov 16 17:07:10 2017
@@ -32,7 +32,10 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
@@ -41,9 +44,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <functional>
Modified: llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp (original)
+++ llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp Thu Nov 16 17:07:10 2017
@@ -45,6 +45,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/LLVMContext.h"
@@ -52,9 +55,6 @@
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Thu Nov 16 17:07:10 2017
@@ -42,6 +42,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/BranchProbability.h"
@@ -50,9 +53,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <tuple>
Modified: llvm/trunk/lib/CodeGen/InterferenceCache.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InterferenceCache.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InterferenceCache.cpp (original)
+++ llvm/trunk/lib/CodeGen/InterferenceCache.cpp Thu Nov 16 17:07:10 2017
@@ -20,9 +20,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <cstdlib>
Modified: llvm/trunk/lib/CodeGen/InterleavedAccessPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InterleavedAccessPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InterleavedAccessPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/InterleavedAccessPass.cpp Thu Nov 16 17:07:10 2017
@@ -48,7 +48,9 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
@@ -63,9 +65,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,7 @@
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/IRPrintingPasses.h"
#include "llvm/IR/LegacyPassManager.h"
@@ -31,7 +32,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
Modified: llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugValues.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugValues.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugValues.cpp Thu Nov 16 17:07:10 2017
@@ -38,6 +38,9 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -48,9 +51,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Thu Nov 16 17:07:10 2017
@@ -40,6 +40,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -52,9 +55,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Thu Nov 16 17:07:10 2017
@@ -32,11 +32,11 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Nov 16 17:07:10 2017
@@ -34,6 +34,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -44,8 +46,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Thu Nov 16 17:07:10 2017
@@ -17,8 +17,8 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdlib>
Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Thu Nov 16 17:07:10 2017
@@ -24,10 +24,10 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp Thu Nov 16 17:07:10 2017
@@ -21,13 +21,13 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp Thu Nov 16 17:07:10 2017
@@ -18,14 +18,14 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveIntervalUnion.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/LiveRegUnits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRegUnits.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRegUnits.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRegUnits.cpp Thu Nov 16 17:07:10 2017
@@ -19,8 +19,8 @@
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "livestacks"
Modified: llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp (original)
+++ llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Thu Nov 16 17:07:10 2017
@@ -26,14 +26,14 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackProtector.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/LowerEmuTLS.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerEmuTLS.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerEmuTLS.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerEmuTLS.cpp Thu Nov 16 17:07:10 2017
@@ -16,11 +16,11 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Thu Nov 16 17:07:10 2017
@@ -37,6 +37,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
@@ -67,8 +69,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cctype>
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -35,6 +35,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfo.h"
@@ -62,8 +64,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cinttypes>
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Nov 16 17:07:10 2017
@@ -22,6 +22,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfoMetadata.h"
@@ -32,8 +34,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Thu Nov 16 17:07:10 2017
@@ -44,7 +44,9 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/TailDuplicator.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Pass.h"
@@ -56,9 +58,7 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
@@ -36,9 +39,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/RecyclingAllocator.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/MachineCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCombiner.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCombiner.cpp Thu Nov 16 17:07:10 2017
@@ -22,12 +22,12 @@
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp Thu Nov 16 17:07:10 2017
@@ -24,12 +24,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp Thu Nov 16 17:07:10 2017
@@ -18,10 +18,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#define DEBUG_TYPE "codegen"
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,10 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
@@ -58,11 +62,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Nov 16 17:07:10 2017
@@ -34,6 +34,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -61,8 +63,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp Thu Nov 16 17:07:10 2017
@@ -14,9 +14,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Nov 16 17:07:10 2017
@@ -35,7 +35,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -44,9 +47,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <limits>
Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Thu Nov 16 17:07:10 2017
@@ -15,6 +15,7 @@
#include "llvm/ADT/TinyPtrVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DerivedTypes.h"
@@ -27,7 +28,6 @@
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/MachineOutliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOutliner.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineOutliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineOutliner.cpp Thu Nov 16 17:07:10 2017
@@ -66,13 +66,13 @@
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <functional>
#include <map>
#include <sstream>
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Thu Nov 16 17:07:10 2017
@@ -90,6 +90,9 @@
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -103,9 +106,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <climits>
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -29,8 +31,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Thu Nov 16 17:07:10 2017
@@ -22,12 +22,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/SSAUpdaterImpl.h"
#include <utility>
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Thu Nov 16 17:07:10 2017
@@ -43,8 +43,11 @@
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
@@ -53,9 +56,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Thu Nov 16 17:07:10 2017
@@ -34,6 +34,8 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Pass.h"
@@ -41,8 +43,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp Thu Nov 16 17:07:10 2017
@@ -22,15 +22,15 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Nov 16 17:07:10 2017
@@ -52,6 +52,9 @@
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
@@ -68,9 +71,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizePHIs.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/OptimizePHIs.cpp (original)
+++ llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Thu Nov 16 17:07:10 2017
@@ -21,9 +21,9 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Nov 16 17:07:10 2017
@@ -32,13 +32,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/PatchableFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PatchableFunction.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PatchableFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/PatchableFunction.cpp Thu Nov 16 17:07:10 2017
@@ -18,7 +18,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -82,6 +82,9 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -89,9 +92,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <memory>
Modified: llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp Thu Nov 16 17:07:10 2017
@@ -32,10 +32,10 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "post-RA-hazard-rec"
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Nov 16 17:07:10 2017
@@ -35,14 +35,14 @@
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "post-RA-sched"
Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Thu Nov 16 17:07:10 2017
@@ -14,9 +14,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Thu Nov 16 17:07:10 2017
@@ -41,6 +41,9 @@
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -58,10 +61,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/RegAllocBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBase.cpp Thu Nov 16 17:07:10 2017
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
@@ -28,7 +29,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Thu Nov 16 17:07:10 2017
@@ -29,11 +29,11 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/PassAnalysisSupport.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdlib>
#include <queue>
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Thu Nov 16 17:07:10 2017
@@ -31,6 +31,9 @@
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Metadata.h"
@@ -42,9 +45,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <tuple>
#include <vector>
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Thu Nov 16 17:07:10 2017
@@ -55,6 +55,8 @@
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
@@ -68,8 +70,6 @@
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Thu Nov 16 17:07:10 2017
@@ -59,6 +59,8 @@
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
@@ -70,8 +72,6 @@
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Thu Nov 16 17:07:10 2017
@@ -20,13 +20,13 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Nov 16 17:07:10 2017
@@ -36,6 +36,9 @@
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -46,9 +49,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/RegisterPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterPressure.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp Thu Nov 16 17:07:10 2017
@@ -26,14 +26,14 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Nov 16 17:07:10 2017
@@ -30,13 +30,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp Thu Nov 16 17:07:10 2017
@@ -12,17 +12,17 @@
///
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SafeStack.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SafeStack.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SafeStack.cpp (original)
+++ llvm/trunk/lib/CodeGen/SafeStack.cpp Thu Nov 16 17:07:10 2017
@@ -28,7 +28,9 @@
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallSite.h"
@@ -57,9 +59,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,7 @@
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
@@ -31,7 +32,6 @@
#include "llvm/IR/Value.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Thu Nov 16 17:07:10 2017
@@ -20,12 +20,12 @@
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Nov 16 17:07:10 2017
@@ -36,6 +36,8 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Instruction.h"
@@ -52,8 +54,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -16,11 +16,11 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <fstream>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 16 17:07:10 2017
@@ -42,6 +42,9 @@
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
@@ -59,11 +62,8 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Nov 16 17:07:10 2017
@@ -64,6 +64,8 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -99,10 +101,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu Nov 16 17:07:10 2017
@@ -21,6 +21,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
@@ -34,10 +37,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Nov 16 17:07:10 2017
@@ -22,13 +22,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "instr-emitter"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Nov 16 17:07:10 2017
@@ -26,6 +26,9 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
@@ -40,11 +43,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Nov 16 17:07:10 2017
@@ -35,13 +35,13 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Thu Nov 16 17:07:10 2017
@@ -22,12 +22,12 @@
#include "llvm/CodeGen/ResourcePriorityQueue.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Thu Nov 16 17:07:10 2017
@@ -19,12 +19,12 @@
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "pre-RA-sched"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,10 @@
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -43,10 +47,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Nov 16 17:07:10 2017
@@ -24,13 +24,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "pre-RA-sched"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp Thu Nov 16 17:07:10 2017
@@ -26,12 +26,12 @@
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <climits>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 16 17:07:10 2017
@@ -37,6 +37,9 @@
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
@@ -59,11 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Mutex.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp Thu Nov 16 17:07:10 2017
@@ -13,8 +13,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Target/TargetLowering.h"
#include <cstdint>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Nov 16 17:07:10 2017
@@ -57,6 +57,10 @@
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Argument.h"
@@ -101,12 +105,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Thu Nov 16 17:07:10 2017
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/DebugLoc.h"
@@ -32,7 +33,6 @@
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLowering.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Thu Nov 16 17:07:10 2017
@@ -24,6 +24,9 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@@ -40,10 +43,7 @@
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Nov 16 17:07:10 2017
@@ -49,6 +49,9 @@
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@@ -82,11 +85,8 @@
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -18,13 +18,13 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "dag-printer"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/StatepointLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/StatepointLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/StatepointLowering.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,8 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Instruction.h"
@@ -41,9 +43,7 @@
#include "llvm/IR/Statepoint.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Nov 16 17:07:10 2017
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/CallingConvLower.h"
@@ -20,6 +20,9 @@
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/GlobalVariable.h"
@@ -29,10 +32,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cctype>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrap.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ShrinkWrap.cpp (original)
+++ llvm/trunk/lib/CodeGen/ShrinkWrap.cpp Thu Nov 16 17:07:10 2017
@@ -67,6 +67,8 @@
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -76,8 +78,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <memory>
Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Thu Nov 16 17:07:10 2017
@@ -35,6 +35,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/LaneBitmask.h"
@@ -44,9 +47,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/StackColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackColoring.cpp Thu Nov 16 17:07:10 2017
@@ -40,6 +40,7 @@
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackProtector.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfoMetadata.h"
@@ -54,7 +55,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
#include <algorithm>
#include <cassert>
#include <limits>
Modified: llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp Thu Nov 16 17:07:10 2017
@@ -19,10 +19,10 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/StackMaps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackMaps.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackMaps.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackMaps.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
@@ -27,9 +30,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/StackProtector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackProtector.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackProtector.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackProtector.cpp Thu Nov 16 17:07:10 2017
@@ -14,14 +14,16 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/StackProtector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/Analysis/EHPersonalities.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/StackProtector.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@@ -42,10 +44,8 @@
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Thu Nov 16 17:07:10 2017
@@ -29,13 +29,13 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/TailDuplicator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplicator.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplicator.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplicator.cpp Thu Nov 16 17:07:10 2017
@@ -29,14 +29,14 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp Thu Nov 16 17:07:10 2017
@@ -15,16 +15,16 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Compiler.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,8 @@
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -27,9 +29,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cctype>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Nov 16 17:07:10 2017
@@ -31,6 +31,9 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -48,15 +51,12 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
-#include <cstring>
#include <cstddef>
#include <cstdint>
+#include <cstring>
#include <iterator>
#include <string>
#include <tuple>
Modified: llvm/trunk/lib/CodeGen/TargetOptionsImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetOptionsImpl.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetOptionsImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetOptionsImpl.cpp Thu Nov 16 17:07:10 2017
@@ -13,11 +13,11 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
/// DisableFramePointerElim - This returns true if frame pointer elimination
Modified: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp Thu Nov 16 17:07:10 2017
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
@@ -18,6 +19,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -27,9 +30,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Thu Nov 16 17:07:10 2017
@@ -17,14 +17,14 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp Thu Nov 16 17:07:10 2017
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Nov 16 17:07:10 2017
@@ -47,6 +47,9 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Pass.h"
@@ -56,9 +59,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Nov 16 17:07:10 2017
@@ -32,14 +32,14 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp (original)
+++ llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp Thu Nov 16 17:07:10 2017
@@ -24,11 +24,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/Pass.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/LTO/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/LTO/LTOCodeGenerator.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/LTO/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/lib/LTO/LTOCodeGenerator.cpp Thu Nov 16 17:07:10 2017
@@ -22,6 +22,9 @@
#include "llvm/Bitcode/BitcodeWriter.h"
#include "llvm/CodeGen/ParallelCG.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Config/config.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
@@ -52,10 +55,7 @@
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Support/YAMLTraits.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/IPO/Internalize.h"
#include "llvm/Transforms/IPO/PassManagerBuilder.h"
Modified: llvm/trunk/lib/LTO/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/LTO/LTOModule.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/LTO/LTOModule.cpp (original)
+++ llvm/trunk/lib/LTO/LTOModule.cpp Thu Nov 16 17:07:10 2017
@@ -16,6 +16,10 @@
#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/ObjectUtils.h"
#include "llvm/Bitcode/BitcodeReader.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/LLVMContext.h"
@@ -40,10 +44,6 @@
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/GlobalStatus.h"
#include <system_error>
using namespace llvm;
Modified: llvm/trunk/lib/LTO/UpdateCompilerUsed.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/LTO/UpdateCompilerUsed.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/LTO/UpdateCompilerUsed.cpp (original)
+++ llvm/trunk/lib/LTO/UpdateCompilerUsed.cpp Thu Nov 16 17:07:10 2017
@@ -13,10 +13,10 @@
#include "llvm/LTO/legacy/UpdateCompilerUsed.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Mangler.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/IPO/Internalize.h"
#include "llvm/Transforms/Utils/ModuleUtils.h"
Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -46,7 +47,6 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Thu Nov 16 17:07:10 2017
@@ -32,14 +32,14 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp Thu Nov 16 17:07:10 2017
@@ -113,11 +113,11 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64-collect-loh"
Modified: llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp Thu Nov 16 17:07:10 2017
@@ -35,10 +35,10 @@
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -74,11 +74,11 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdlib>
#include <tuple>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp Thu Nov 16 17:07:10 2017
@@ -32,11 +32,11 @@
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp Thu Nov 16 17:07:10 2017
@@ -21,9 +21,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64-dead-defs"
Modified: llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp Thu Nov 16 17:07:10 2017
@@ -27,13 +27,13 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Thu Nov 16 17:07:10 2017
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
@@ -46,7 +47,6 @@
#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -111,6 +111,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DataLayout.h"
@@ -124,8 +126,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -42,6 +42,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
@@ -71,7 +72,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "AArch64.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Instruction.h"
-#include "llvm/Target/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCInst.h"
@@ -41,8 +43,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Nov 16 17:07:10 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h"
-#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
@@ -34,7 +35,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp Thu Nov 16 17:07:10 2017
@@ -18,13 +18,13 @@
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Nov 16 17:07:10 2017
@@ -22,10 +22,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Nov 16 17:07:10 2017
@@ -23,8 +23,8 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -35,7 +36,6 @@
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
#include <memory>
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetObjectFile.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetObjectFile.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetObjectFile.h Thu Nov 16 17:07:10 2017
@@ -10,8 +10,8 @@
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETOBJECTFILE_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETOBJECTFILE_H
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
namespace llvm {
class AArch64TargetMachine;
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -12,10 +12,10 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/CostTable.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
-#include "llvm/Target/TargetLowering.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp Thu Nov 16 17:07:10 2017
@@ -35,10 +35,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
using namespace llvm;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,7 @@
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCSectionELF.h"
@@ -39,7 +40,6 @@
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
using namespace llvm::AMDGPU;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h Thu Nov 16 17:07:10 2017
@@ -18,7 +18,7 @@
#include "AMDGPU.h"
#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Nov 16 17:07:10 2017
@@ -13,11 +13,11 @@
//===----------------------------------------------------------------------===//
#include "AMDGPULegalizerInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp Thu Nov 16 17:07:10 2017
@@ -29,14 +29,14 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegionInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <tuple>
#include <utility>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_TARGET_REGBANK_IMPL
#include "AMDGPUGenRegisterBank.inc"
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -39,7 +40,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/IPO/AlwaysInliner.h"
#include "llvm/Transforms/IPO/PassManagerBuilder.h"
Modified: llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp Thu Nov 16 17:07:10 2017
@@ -18,12 +18,12 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -30,9 +30,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp Thu Nov 16 17:07:10 2017
@@ -81,13 +81,13 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp Thu Nov 16 17:07:10 2017
@@ -60,7 +60,7 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -52,6 +52,8 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
@@ -72,9 +74,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cmath>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -41,6 +41,8 @@
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Function.h"
@@ -53,8 +55,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Thu Nov 16 17:07:10 2017
@@ -63,9 +63,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp Thu Nov 16 17:07:10 2017
@@ -25,10 +25,10 @@
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <map>
Modified: llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp Thu Nov 16 17:07:10 2017
@@ -38,12 +38,12 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp Thu Nov 16 17:07:10 2017
@@ -74,13 +74,13 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <vector>
Modified: llvm/trunk/lib/Target/ARC/ARCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARC/ARCAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
@@ -33,7 +34,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARC/ARCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCFrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARC/ARCFrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#define DEBUG_TYPE "arc-frame-lowering"
Modified: llvm/trunk/lib/Target/ARC/ARCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCISelDAGToDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARC/ARCISelDAGToDAG.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
@@ -29,7 +30,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARC/ARCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARC/ARCISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "ARC.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/ARC/ARCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARC/ARCRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_ARC_ARCREGISTERINFO_H
#define LLVM_LIB_TARGET_ARC_ARCREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "ARCGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/ARC/ARCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARC/ARCSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,7 +18,7 @@
#include "ARCISelLowering.h"
#include "ARCInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -34,10 +34,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
#include <set>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -38,6 +38,7 @@
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
@@ -55,7 +56,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
@@ -44,7 +45,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <utility>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -17,9 +17,9 @@
#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdint>
#define GET_REGINFO_HEADER
Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -41,8 +43,6 @@
#include "llvm/IR/Value.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include <vector>
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Nov 16 17:07:10 2017
@@ -44,6 +44,9 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -73,11 +76,8 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <utility>
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -35,6 +35,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
@@ -51,10 +54,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp Thu Nov 16 17:07:10 2017
@@ -13,7 +13,7 @@
#include "ARMSubtarget.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Nov 16 17:07:10 2017
@@ -12,10 +12,10 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
-#include "Utils/ARMBaseInfo.h"
#include "ARMBaseInstrInfo.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
+#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
@@ -32,7 +33,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -58,6 +58,10 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -95,12 +99,8 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Nov 16 17:07:10 2017
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -30,7 +31,6 @@
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/CodeGen.h"
-#include "llvm/Target/TargetLowering.h"
#include <utility>
namespace llvm {
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu Nov 16 17:07:10 2017
@@ -17,10 +17,10 @@
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h"
-#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -43,6 +43,9 @@
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
@@ -55,9 +58,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_TARGET_REGBANK_IMPL
#include "ARMGenRegisterBank.inc"
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Nov 16 17:07:10 2017
@@ -26,10 +26,10 @@
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <memory>
#include <string>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -10,10 +10,10 @@
//
//===----------------------------------------------------------------------===//
+#include "ARMTargetMachine.h"
#include "ARM.h"
-#include "ARMSubtarget.h"
#include "ARMMacroFusion.h"
-#include "ARMTargetMachine.h"
+#include "ARMSubtarget.h"
#include "ARMTargetObjectFile.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMMCTargetDesc.h"
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -44,7 +45,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
#include <cassert>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -13,6 +13,7 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ValueTypes.h"
@@ -25,7 +26,6 @@
#include "llvm/IR/Type.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Target/CostTable.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp Thu Nov 16 17:07:10 2017
@@ -21,10 +21,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "mlx-expansion"
Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDwarf.h"
@@ -39,8 +41,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <bitset>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -11,9 +11,9 @@
//
//===----------------------------------------------------------------------===//
+#include "Thumb2InstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
-#include "Thumb2InstrInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -29,7 +30,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
#include "ARMBaseRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
namespace llvm {
class ARMSubtarget;
Modified: llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -20,6 +20,8 @@
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCStreamer.h"
@@ -27,8 +29,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define DEBUG_TYPE "avr-asm-printer"
Modified: llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp Thu Nov 16 17:07:10 2017
@@ -22,7 +22,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AVR/AVRISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRISelLowering.h (original)
+++ llvm/trunk/lib/Target/AVR/AVRISelLowering.h Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#define LLVM_AVR_ISEL_LOWERING_H
#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_AVR_REGISTER_INFO_H
#define LLVM_AVR_REGISTER_INFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "AVRGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/AVR/AVRRelaxMemOperations.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRelaxMemOperations.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRRelaxMemOperations.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRRelaxMemOperations.cpp Thu Nov 16 17:07:10 2017
@@ -20,7 +20,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AVR/AVRSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRSubtarget.h (original)
+++ llvm/trunk/lib/Target/AVR/AVRSubtarget.h Thu Nov 16 17:07:10 2017
@@ -14,9 +14,9 @@
#ifndef LLVM_AVR_SUBTARGET_H
#define LLVM_AVR_SUBTARGET_H
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "AVRFrameLowering.h"
#include "AVRISelLowering.h"
Modified: llvm/trunk/lib/Target/BPF/BPFISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFISelLowering.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "BPF.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
class BPFSubtarget;
Modified: llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_BPF_BPFREGISTERINFO_H
#define LLVM_LIB_TARGET_BPF_BPFREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "BPFGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/BPF/BPFSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFSubtarget.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "BPFISelLowering.h"
#include "BPFInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "BPFGenSubtargetInfo.inc"
Modified: llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/BitTracker.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/BitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/BitTracker.cpp Thu Nov 16 17:07:10 2017
@@ -61,10 +61,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.h (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.h Thu Nov 16 17:07:10 2017
@@ -43,7 +43,7 @@
#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -31,6 +31,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCExpr.h"
@@ -44,8 +46,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Thu Nov 16 17:07:10 2017
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -35,7 +36,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Thu Nov 16 17:07:10 2017
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -26,7 +27,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp Thu Nov 16 17:07:10 2017
@@ -17,10 +17,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp Thu Nov 16 17:07:10 2017
@@ -15,9 +15,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <vector>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp Thu Nov 16 17:07:10 2017
@@ -25,6 +25,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
@@ -34,8 +36,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <cstring>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp Thu Nov 16 17:07:10 2017
@@ -21,12 +21,12 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/PassSupport.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Thu Nov 16 17:07:10 2017
@@ -76,6 +76,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/BranchProbability.h"
@@ -84,7 +85,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Thu Nov 16 17:07:10 2017
@@ -103,6 +103,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/LaneBitmask.h"
@@ -111,8 +113,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <set>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -38,6 +38,7 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -53,7 +54,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Thu Nov 16 17:07:10 2017
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
@@ -35,7 +36,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Thu Nov 16 17:07:10 2017
@@ -19,13 +19,13 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <iterator>
#include <map>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Thu Nov 16 17:07:10 2017
@@ -42,6 +42,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
@@ -50,7 +51,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <cstdlib>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CallingConv.h"
@@ -50,7 +51,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Thu Nov 16 17:07:10 2017
@@ -20,10 +20,10 @@
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/InlineAsm.h"
-#include "llvm/Target/TargetLowering.h"
#include <cstdint>
#include <utility>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -37,6 +37,9 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -49,9 +52,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cctype>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Thu Nov 16 17:07:10 2017
@@ -25,14 +25,14 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iomanip>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h Thu Nov 16 17:07:10 2017
@@ -22,7 +22,7 @@
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <limits>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -42,9 +45,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Thu Nov 16 17:07:10 2017
@@ -27,13 +27,13 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Thu Nov 16 17:07:10 2017
@@ -45,13 +45,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/PassSupport.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -15,7 +15,7 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "HexagonGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp Thu Nov 16 17:07:10 2017
@@ -24,7 +24,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp Thu Nov 16 17:07:10 2017
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
@@ -32,7 +33,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Thu Nov 16 17:07:10 2017
@@ -23,8 +23,8 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <memory>
#include <string>
#include <vector>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Thu Nov 16 17:07:10 2017
@@ -36,6 +36,8 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -43,8 +45,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp Thu Nov 16 17:07:10 2017
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Pass.h"
@@ -29,7 +30,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
#include <string>
#include <vector>
Modified: llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp Thu Nov 16 17:07:10 2017
@@ -18,13 +18,13 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <utility>
Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp Thu Nov 16 17:07:10 2017
@@ -22,6 +22,9 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -29,9 +32,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp Thu Nov 16 17:07:10 2017
@@ -34,13 +34,13 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp Thu Nov 16 17:07:10 2017
@@ -12,11 +12,11 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <set>
Modified: llvm/trunk/lib/Target/Hexagon/RDFRegisters.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFRegisters.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFRegisters.h (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFRegisters.h Thu Nov 16 17:07:10 2017
@@ -12,8 +12,8 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/LaneBitmask.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <map>
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DerivedTypes.h"
@@ -45,7 +46,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <cmath>
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h Thu Nov 16 17:07:10 2017
@@ -18,7 +18,7 @@
#include "Lanai.h"
#include "LanaiRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
namespace LanaiISD {
Modified: llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H
#define LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "LanaiGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Lanai/LanaiSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiSubtarget.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,10 +18,10 @@
#include "LanaiISelLowering.h"
#include "LanaiInstrInfo.h"
#include "LanaiSelectionDAGInfo.h"
-#include "llvm/IR/DataLayout.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "LanaiGenSubtargetInfo.inc"
Modified: llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h Thu Nov 16 17:07:10 2017
@@ -22,8 +22,8 @@
#include "LanaiTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
namespace llvm {
class LanaiTTIImpl : public BasicTTIImplBase<LanaiTTIImpl> {
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
@@ -27,7 +28,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "msp430-isel"
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "MSP430.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
namespace MSP430ISD {
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_MSP430_MSP430REGISTERINFO_H
#define LLVM_LIB_TARGET_MSP430_MSP430REGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "MSP430GenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Thu Nov 16 17:07:10 2017
@@ -19,8 +19,8 @@
#include "MSP430InstrInfo.h"
#include "MSP430RegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -21,13 +21,13 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cctype>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -36,6 +36,8 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DataLayout.h"
@@ -55,8 +57,6 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <map>
Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Thu Nov 16 17:07:10 2017
@@ -34,6 +34,8 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
@@ -41,8 +43,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Thu Nov 16 17:07:10 2017
@@ -38,6 +38,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -65,7 +66,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -47,6 +47,7 @@
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
@@ -66,7 +67,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cctype>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Nov 16 17:07:10 2017
@@ -24,11 +24,11 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Type.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -22,11 +22,11 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp Thu Nov 16 17:07:10 2017
@@ -31,12 +31,12 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp Thu Nov 16 17:07:10 2017
@@ -14,8 +14,8 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp Thu Nov 16 17:07:10 2017
@@ -29,13 +29,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/RecyclingAllocator.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <utility>
#include <vector>
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Nov 16 17:07:10 2017
@@ -23,14 +23,14 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cstdint>
using namespace llvm;
Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -30,6 +30,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
@@ -38,8 +40,6 @@
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <utility>
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Intrinsics.h"
@@ -41,7 +42,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Thu Nov 16 17:07:10 2017
@@ -19,10 +19,10 @@
#include "MipsISelLowering.h"
#include "MipsInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -45,6 +45,9 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
@@ -75,10 +78,7 @@
#include "llvm/Support/Path.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Transforms/Utils/UnrollLoop.h"
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,8 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -49,8 +51,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetCallingConv.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "NVPTX.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
namespace NVPTXISD {
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp Thu Nov 16 17:07:10 2017
@@ -37,7 +37,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp Thu Nov 16 17:07:10 2017
@@ -17,12 +17,12 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_NVPTX_NVPTXREGISTERINFO_H
#include "ManagedStringPool.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include <sstream>
#define GET_REGINFO_HEADER
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h Thu Nov 16 17:07:10 2017
@@ -20,8 +20,8 @@
#include "NVPTXInstrInfo.h"
#include "NVPTXRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h Thu Nov 16 17:07:10 2017
@@ -11,9 +11,9 @@
#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETOBJECTFILE_H
#include "NVPTXSection.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/MC/MCSection.h"
#include "llvm/MC/SectionKind.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -13,9 +13,9 @@
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/CostTable.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "NVPTXtti"
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetTransformInfo.h Thu Nov 16 17:07:10 2017
@@ -21,7 +21,7 @@
#include "NVPTXTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
#include "Nios2.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "Nios2GenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h (original)
+++ llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#include "Nios2FrameLowering.h"
#include "Nios2InstrInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "Nios2GenSubtargetInfo.inc"
Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -15,6 +15,7 @@
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPCInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -23,7 +24,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp Thu Nov 16 17:07:10 2017
@@ -23,8 +23,8 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Nov 16 17:07:10 2017
@@ -23,9 +23,9 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "ppc-branch-select"
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/GlobalAlias.h"
@@ -36,7 +37,6 @@
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Operator.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Nov 16 17:07:10 2017
@@ -37,6 +37,7 @@
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
@@ -54,7 +55,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -52,6 +52,8 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
@@ -83,10 +85,8 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Nov 16 17:07:10 2017
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -30,7 +31,6 @@
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Type.h"
-#include "llvm/Target/TargetLowering.h"
#include <utility>
namespace llvm {
Modified: llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp Thu Nov 16 17:07:10 2017
@@ -20,14 +20,14 @@
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
static MachineModuleInfoMachO &getMachOMMI(AsmPrinter &AP) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/TargetCallingConv.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp Thu Nov 16 17:07:10 2017
@@ -22,9 +22,9 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "ppc-qpx-load-splat"
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Thu Nov 16 17:07:10 2017
@@ -19,9 +19,9 @@
#include "PPCInstrInfo.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -23,6 +23,7 @@
#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -31,7 +32,6 @@
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
#include <cassert>
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetObjectFile.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetObjectFile.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetObjectFile.h Thu Nov 16 17:07:10 2017
@@ -10,8 +10,8 @@
#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETOBJECTFILE_H
#define LLVM_LIB_TARGET_POWERPC_PPCTARGETOBJECTFILE_H
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -10,10 +10,10 @@
#include "PPCTargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/CostTable.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "ppctti"
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h Thu Nov 16 17:07:10 2017
@@ -21,7 +21,7 @@
#include "PPCTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "RISCV.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
class RISCVSubtarget;
Modified: llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "RISCVGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "RISCVISelLowering.h"
#include "RISCVInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "RISCVGenSubtargetInfo.inc"
Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Thu Nov 16 17:07:10 2017
@@ -20,9 +20,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
#include "Sparc.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
class SparcSubtarget;
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H
#define LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "SparcGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "SparcISelLowering.h"
#include "SparcInstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
-#include "llvm/IR/DataLayout.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DataLayout.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetObjectFile.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetObjectFile.cpp Thu Nov 16 17:07:10 2017
@@ -11,7 +11,7 @@
#include "MCTargetDesc/SparcMCExpr.h"
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp Thu Nov 16 17:07:10 2017
@@ -25,9 +25,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Thu Nov 16 17:07:10 2017
@@ -18,7 +18,7 @@
#include "SystemZ.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
namespace SystemZISD {
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Thu Nov 16 17:07:10 2017
@@ -29,13 +29,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp Thu Nov 16 17:07:10 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -11,7 +11,7 @@
#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
#include "SystemZ.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "SystemZGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Thu Nov 16 17:07:10 2017
@@ -20,8 +20,8 @@
#include "SystemZRegisterInfo.h"
#include "SystemZSelectionDAGInfo.h"
#include "llvm/ADT/Triple.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -18,12 +18,12 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Transforms/Scalar.h"
#include <string>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -17,10 +17,10 @@
#include "SystemZTargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/CostTable.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "systemztti"
Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Thu Nov 16 17:07:10 2017
@@ -12,8 +12,10 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
@@ -27,10 +29,8 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -14,6 +14,9 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
@@ -26,9 +29,6 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/SectionKind.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
//---------------------------------------------------------------------------
Modified: llvm/trunk/lib/Target/TargetMachineC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachineC.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachineC.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachineC.cpp Thu Nov 16 17:07:10 2017
@@ -15,6 +15,7 @@
#include "llvm-c/Target.h"
#include "llvm-c/TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Module.h"
@@ -25,7 +26,6 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdlib>
#include <cstring>
Modified: llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -18,6 +18,7 @@
#include "WebAssemblyMachineFunctionInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -25,7 +26,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h Thu Nov 16 17:07:10 2017
@@ -20,7 +20,7 @@
#include "WebAssemblyISelLowering.h"
#include "WebAssemblyInstrInfo.h"
#include "WebAssemblySelectionDAGInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -14,8 +14,8 @@
//===----------------------------------------------------------------------===//
#include "WebAssemblyTargetTransformInfo.h"
+#include "llvm/CodeGen/CostTable.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
using namespace llvm;
#define DEBUG_TYPE "wasmtti"
Modified: llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp Thu Nov 16 17:07:10 2017
@@ -35,13 +35,13 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Thu Nov 16 17:07:10 2017
@@ -35,6 +35,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -42,7 +43,6 @@
#include "llvm/IR/Value.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CmovConversion.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CmovConversion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CmovConversion.cpp Thu Nov 16 17:07:10 2017
@@ -58,15 +58,15 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
Modified: llvm/trunk/lib/Target/X86/X86DomainReassignment.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86DomainReassignment.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86DomainReassignment.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86DomainReassignment.cpp Thu Nov 16 17:07:10 2017
@@ -25,8 +25,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Thu Nov 16 17:07:10 2017
@@ -38,12 +38,12 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <bitset>
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Nov 16 17:07:10 2017
@@ -35,6 +35,7 @@
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
@@ -55,7 +56,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <bitset>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Thu Nov 16 17:07:10 2017
@@ -31,6 +31,8 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/Support/AtomicOrdering.h"
@@ -40,8 +42,6 @@
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <tuple>
Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Thu Nov 16 17:07:10 2017
@@ -14,10 +14,10 @@
#include "X86LegalizerInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h"
-#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
using namespace TargetOpcode;
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Thu Nov 16 17:07:10 2017
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Mangler.h"
@@ -46,7 +47,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.cpp Thu Nov 16 17:07:10 2017
@@ -10,7 +10,7 @@
#include "X86MachineFunctionInfo.h"
#include "X86RegisterInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86OptimizeLEAs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86OptimizeLEAs.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86OptimizeLEAs.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86OptimizeLEAs.cpp Thu Nov 16 17:07:10 2017
@@ -33,6 +33,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -42,8 +44,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp Thu Nov 16 17:07:10 2017
@@ -16,7 +16,7 @@
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_TARGET_REGBANK_IMPL
#include "X86GenRegisterBank.inc"
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "X86GenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Thu Nov 16 17:07:10 2017
@@ -17,8 +17,8 @@
#include "X86RegisterInfo.h"
#include "X86Subtarget.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/DerivedTypes.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Nov 16 17:07:10 2017
@@ -24,10 +24,10 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <memory>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Nov 16 17:07:10 2017
@@ -11,13 +11,13 @@
//
//===----------------------------------------------------------------------===//
+#include "X86TargetMachine.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "X86.h"
#include "X86CallLowering.h"
#include "X86LegalizerInfo.h"
#include "X86MacroFusion.h"
#include "X86Subtarget.h"
-#include "X86TargetMachine.h"
#include "X86TargetObjectFile.h"
#include "X86TargetTransformInfo.h"
#include "llvm/ADT/Optional.h"
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -43,7 +44,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include <memory>
#include <string>
Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp Thu Nov 16 17:07:10 2017
@@ -11,6 +11,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/COFF.h"
#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/Mangler.h"
#include "llvm/IR/Operator.h"
#include "llvm/MC/MCContext.h"
@@ -18,7 +19,6 @@
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
using namespace dwarf;
Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetObjectFile.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.h Thu Nov 16 17:07:10 2017
@@ -10,8 +10,8 @@
#ifndef LLVM_LIB_TARGET_X86_X86TARGETOBJECTFILE_H
#define LLVM_LIB_TARGET_X86_X86TARGETOBJECTFILE_H
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Thu Nov 16 17:07:10 2017
@@ -42,10 +42,10 @@
#include "X86TargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/CostTable.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/CostTable.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h Thu Nov 16 17:07:10 2017
@@ -21,7 +21,7 @@
#include "X86TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp Thu Nov 16 17:07:10 2017
@@ -27,13 +27,13 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Thu Nov 16 17:07:10 2017
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFile.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
@@ -41,7 +42,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include <algorithm>
#include <cctype>
using namespace llvm;
Modified: llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp Thu Nov 16 17:07:10 2017
@@ -23,12 +23,12 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
-#include <algorithm> // std::sort
+#include <algorithm> // std::sort
using namespace llvm;
Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Thu Nov 16 17:07:10 2017
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
@@ -28,7 +29,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetLowering.h"
using namespace llvm;
/// XCoreDAGToDAGISel - XCore specific code to select XCore machine
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Thu Nov 16 17:07:10 2017
@@ -17,7 +17,7 @@
#include "XCore.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp Thu Nov 16 17:07:10 2017
@@ -9,8 +9,8 @@
#include "XCoreMachineFunctionInfo.h"
#include "XCoreInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Function.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Thu Nov 16 17:07:10 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H
#define LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "XCoreGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h Thu Nov 16 17:07:10 2017
@@ -18,9 +18,9 @@
#include "XCoreISelLowering.h"
#include "XCoreInstrInfo.h"
#include "XCoreSelectionDAGInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
Modified: llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h Thu Nov 16 17:07:10 2017
@@ -21,7 +21,7 @@
#include "XCoreTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
Modified: llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp Thu Nov 16 17:07:10 2017
@@ -166,6 +166,7 @@
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
@@ -188,7 +189,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Local.h"
#include <cassert>
Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Thu Nov 16 17:07:10 2017
@@ -13,7 +13,6 @@
//
//===----------------------------------------------------------------------===//
-
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
@@ -24,6 +23,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
@@ -49,7 +49,6 @@
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include <memory>
using namespace llvm;
Modified: llvm/trunk/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp Thu Nov 16 17:07:10 2017
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/Target/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
#include "gtest/gtest.h"
using namespace llvm;
Modified: llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp Thu Nov 16 17:07:10 2017
@@ -12,12 +12,12 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "gtest/gtest.h"
using namespace llvm;
Modified: llvm/trunk/unittests/MI/LiveIntervalTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MI/LiveIntervalTest.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/unittests/MI/LiveIntervalTest.cpp (original)
+++ llvm/trunk/unittests/MI/LiveIntervalTest.cpp Thu Nov 16 17:07:10 2017
@@ -5,6 +5,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/SourceMgr.h"
@@ -12,7 +13,6 @@
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include "gtest/gtest.h"
using namespace llvm;
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Nov 16 17:07:10 2017
@@ -348,7 +348,7 @@ GetInstByName(const char *Name,
void CodeGenTarget::ComputeInstrsByEnum() const {
static const char *const FixedInstrs[] = {
#define HANDLE_TARGET_OPCODE(OPC) #OPC,
-#include "llvm/Target/TargetOpcodes.def"
+#include "llvm/CodeGen/TargetOpcodes.def"
nullptr};
const auto &Insts = getInstructions();
for (const char *const *p = FixedInstrs; *p; ++p) {
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=318490&r1=318489&r2=318490&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Nov 16 17:07:10 2017
@@ -1102,7 +1102,7 @@ RegisterInfoEmitter::runTargetHeader(raw
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
- OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
+ OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n";
OS << "namespace llvm {\n\n";
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