[PATCH] D40137: [ARM] 't' asm constraint should accept i32

[Yi Kong via Phabricator via llvm-commits]

kongyi updated this revision to Diff 123245.

Repository:
  rL LLVM

https://reviews.llvm.org/D40137

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/inlineasm.ll


Index: test/CodeGen/ARM/inlineasm.ll
===================================================================
--- test/CodeGen/ARM/inlineasm.ll
+++ test/CodeGen/ARM/inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
+; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define i32 @test1(i32 %tmp54) {
 	%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )		; <i32> [#uses=1]
@@ -9,3 +9,10 @@
 	tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
 	ret void
 }
+
+define float @t-constraint-int(i32 %i) {
+	; CHECK-LABEL: t-constraint-int
+	; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}}
+	%ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)
+	ret float %ret
+}
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -13024,7 +13024,7 @@
         return RCPair(0U, &ARM::QPR_8RegClass);
       break;
     case 't':
-      if (VT == MVT::f32)
+      if (VT == MVT::f32 || VT == MVT::i32)
         return RCPair(0U, &ARM::SPRRegClass);
       break;
     }


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