[PATCH] D39952: [X86]: Adding full coverage of MC encoding for all X86 ISA Sets.NFC

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D39952#924320, @gadi.haber wrote:

> Do you mean the following LWP instructions that belong to the XOP ISA set?:
>  LLWPCB                LLWPCB_GPRvqq                  
>  LWPINS                 LWPINS_GPRyqq_GPRvd_IMMd 
>  LWPINS                 LWPINS_GPRyqq_MEMd_IMMd 
>  LWPVAL                LWPVAL_GPRyqq_GPRvd_IMMd
>  LWPVAL                LWPVAL_GPRyqq_MEMd_IMMd
>  SLWPCB                SLWPCB_GPRvqq


Would it be better to consistently split all these instruction groups by cpuid feature bit instead of ISA set? For instance, LWP uses the XOP encoding but IIRC so does TBM and that is split.


Repository:
  rL LLVM

https://reviews.llvm.org/D39952