[llvm] r318186 - [AArch64] Adjust the cost model for Exynos M1 and M2

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Tue Nov 14 11:59:43 2017
New Revision: 318186

URL: http://llvm.org/viewvc/llvm-project?rev=318186&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M1 and M2

Fix the modeling of loads and stores of registers pairs.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=318186&r1=318185&r2=318186&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Tue Nov 14 11:59:43 2017
@@ -99,6 +99,7 @@ def M1WriteLC : SchedWriteRes<[M1UnitA,
 def M1WriteLD : SchedWriteRes<[M1UnitA,
                                M1UnitL,
                                M1UnitL]> { let Latency = 5; }
+def M1WriteLH : SchedWriteRes<[]>        { let Latency = 5; }
 def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
                                    SchedVar<NoSchedPred,         [M1WriteA1,
                                                                   M1WriteL5]>]>;
@@ -115,9 +116,6 @@ def M1WriteSB : SchedWriteRes<[M1UnitS,
                                M1UnitA]>   { let Latency = 2; }
 def M1WriteSC : SchedWriteRes<[M1UnitS,
                                M1UnitFST,
-                               M1UnitA]>   { let Latency = 1; }
-def M1WriteSD : SchedWriteRes<[M1UnitS,
-                               M1UnitFST,
                                M1UnitS,
                                M1UnitFST,
                                M1UnitA]>   { let Latency = 1; }
@@ -166,7 +164,7 @@ def : SchedAlias<ReadAdrBase, M1ReadAdrB
 
 // Load instructions.
 def : WriteRes<WriteLD,    [M1UnitL]>   { let Latency = 4; }
-def : WriteRes<WriteLDHi,  [M1UnitALU]> { let Latency = 4; }
+def : WriteRes<WriteLDHi,  []>          { let Latency = 4; }
 def : SchedAlias<WriteLDIdx, M1WriteLX>;
 
 // Store instructions.
@@ -188,7 +186,7 @@ def : WriteRes<WriteFImm,  [M1UnitNALU]>
 def : WriteRes<WriteFCopy, [M1UnitS]>    { let Latency = 4; }
 
 // FP load instructions.
-def : WriteRes<WriteVLD, [M1UnitL]> { let Latency = 5; }
+def : WriteRes<WriteVLD,   [M1UnitL]> { let Latency = 5; }
 
 // FP store instructions.
 def : WriteRes<WriteVST, [M1UnitS,
@@ -442,15 +440,15 @@ def : InstRW<[M1WriteLX,
 def : InstRW<[M1WriteLC,
               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 def : InstRW<[WriteVLD,
-              WriteLDHi],   (instregex "^LDN?P[DS]i")>;
+              M1WriteLH],  (instregex "^LDN?P[DS]i")>;
 def : InstRW<[M1WriteLB,
-              WriteLDHi],   (instregex "^LDN?PQi")>;
+              M1WriteLH],  (instregex "^LDN?PQi")>;
 def : InstRW<[M1WriteLC,
-              WriteLDHi,
+              M1WriteLH,
               WriteAdr,
               ReadAdrBase], (instregex "^LDP[DS](post|pre)")>;
 def : InstRW<[M1WriteLD,
-              WriteLDHi,
+              M1WriteLH,
               WriteAdr,
               ReadAdrBase], (instregex "^LDPQ(post|pre)")>;
 
@@ -465,10 +463,10 @@ def : InstRW<[M1WriteSY,
 def : InstRW<[M1WriteSB,
               ReadAdrBase], (instregex "^STRQro[WX]")>;
 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
-def : InstRW<[M1WriteSC,
+def : InstRW<[WriteVST,
               WriteAdr,
               ReadAdrBase], (instregex "^STP[DS](post|pre)")>;
-def : InstRW<[M1WriteSD,
+def : InstRW<[M1WriteSC,
               WriteAdr,
               ReadAdrBase], (instregex "^STPQ(post|pre)")>;