[PATCH] D38196: [AArch64] Avoid interleaved SIMD store instructions for Exynos

[Abderrazek Zaafrani via Phabricator via llvm-commits]

az updated this revision to Diff 122464.
az added a comment.

Code reuse and simplification due to the use of a table that has instruction replacement info.


https://reviews.llvm.org/D38196

Files:
  llvm/lib/Target/AArch64/AArch64.h
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
  llvm/test/CodeGen/AArch64/arm64-st1.ll

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