[PATCH] D39712: [ARM] Add an alias for psr

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai updated this revision to Diff 122023.
xiangzhai added a comment.

The same encoding as GNU Arm Embedded Toolchain <https://developer.arm.com/open-source/gnu-toolchain/gnu-rm>:

  $ arm-none-eabi-gcc -o thumb2-mclass.o -Wall -mlittle-endian -mcpu=cortex-m4 -march=armv7e-m -mthumb -mthumb-interwork -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffreestanding -c test/MC/ARM/thumb2-mclass.s
  
  $ arm-none-eabi-objdump -d thumb2-mclass.o 
  
  thumb2-mclass.o:     file format elf32-littlearm
  
  
  Disassembly of section .text:
  
  00000000 <.text>:
     0:   f3ef 8000       mrs     r0, CPSR
     4:   f3ef 8001       mrs     r0, IAPSR
     8:   f3ef 8002       mrs     r0, EAPSR
     c:   f3ef 8003       mrs     r0, PSR               <-- @ encoding: [0xef,0xf3,0x03,0x80]
    10:   f3ef 8005       mrs     r0, IPSR
    14:   f3ef 8006       mrs     r0, EPSR
    18:   f3ef 8007       mrs     r0, IEPSR
    1c:   f3ef 8008       mrs     r0, MSP
    20:   f3ef 8009       mrs     r0, PSP
    24:   f3ef 8010       mrs     r0, PRIMASK
    28:   f3ef 8014       mrs     r0, CONTROL
    2c:   f3ef 8c03       mrs     ip, PSR               <-- @ encoding: [0xef,0xf3,0x03,0x8c]
    30:   f380 8800       msr     CPSR_f, r0
    34:   f380 8800       msr     CPSR_f, r0
    38:   f380 8801       msr     IAPSR, r0
    3c:   f380 8801       msr     IAPSR, r0
    40:   f380 8802       msr     EAPSR, r0
    44:   f380 8802       msr     EAPSR, r0
    48:   f380 8803       msr     PSR, r0
    4c:   f380 8803       msr     PSR, r0
    50:   f380 8805       msr     IPSR, r0
    54:   f380 8806       msr     EPSR, r0
    58:   f380 8807       msr     IEPSR, r0
    5c:   f380 8808       msr     MSP, r0
    60:   f380 8809       msr     PSP, r0
    64:   f380 8810       msr     PRIMASK, r0
    68:   f380 8814       msr     CONTROL, r0


Repository:
  rL LLVM

https://reviews.llvm.org/D39712

Files:
  lib/Target/ARM/ARMSystemRegister.td
  test/MC/ARM/thumb2-mclass.s


Index: test/MC/ARM/thumb2-mclass.s
===================================================================
--- test/MC/ARM/thumb2-mclass.s
+++ test/MC/ARM/thumb2-mclass.s
@@ -21,6 +21,7 @@
         mrs  r0, psp
         mrs  r0, primask
         mrs  r0, control
+        mrs  ip, psr
 
 @ CHECK: mrs	r0, apsr                @ encoding: [0xef,0xf3,0x00,0x80]
 @ CHECK: mrs	r0, iapsr               @ encoding: [0xef,0xf3,0x01,0x80]
@@ -33,6 +34,7 @@
 @ CHECK: mrs	r0, psp                 @ encoding: [0xef,0xf3,0x09,0x80]
 @ CHECK: mrs	r0, primask             @ encoding: [0xef,0xf3,0x10,0x80]
 @ CHECK: mrs	r0, control             @ encoding: [0xef,0xf3,0x14,0x80]
+@ CHECK: mrs    r12, xpsr               @ encoding: [0xef,0xf3,0x03,0x8c]
 
 @------------------------------------------------------------------------------
 @ MSR
Index: lib/Target/ARM/ARMSystemRegister.td
===================================================================
--- lib/Target/ARM/ARMSystemRegister.td
+++ lib/Target/ARM/ARMSystemRegister.td
@@ -63,6 +63,7 @@
 def : MClassSysReg<1,    1,    0,    0x802, "eapsr_nzcvq">;
 def : MClassSysReg<0,    0,    1,    0x803, "xpsr">;
 def : MClassSysReg<1,    1,    0,    0x803, "xpsr_nzcvq">;
+def : MClassSysReg<1,    0,    1,    0x803, "psr">;
 
 def : MClassSysReg<0,    0,    1,    0x805, "ipsr">;
 def : MClassSysReg<0,    0,    1,    0x806, "epsr">;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D39712.122023.patch
Type: text/x-patch
Size: 1373 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171108/3cd15b0a/attachment.bin>