[llvm] r317647 - Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
David Blaikie via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 7 17:01:32 PST 2017
Author: dblaikie
Date: Tue Nov 7 17:01:31 2017
New Revision: 317647
URL: http://llvm.org/viewvc/llvm-project?rev=317647&view=rev
Log:
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
This header includes CodeGen headers, and is not, itself, included by
any Target headers, so move it into CodeGen to match the layering of its
implementation.
Added:
llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h
- copied, changed from r317645, llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Removed:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
llvm/trunk/include/llvm/CodeGen/TailDuplicator.h
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/Analysis.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/CodeGen/BranchRelaxation.cpp
llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp
llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp
llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/trunk/lib/CodeGen/FEntryInserter.cpp
llvm/trunk/lib/CodeGen/GCRootLowering.cpp
llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
llvm/trunk/lib/CodeGen/InlineSpiller.cpp
llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
llvm/trunk/lib/CodeGen/LiveVariables.cpp
llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
llvm/trunk/lib/CodeGen/MachineCSE.cpp
llvm/trunk/lib/CodeGen/MachineCombiner.cpp
llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/MachineOutliner.cpp
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/MachineSink.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/MacroFusion.cpp
llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
llvm/trunk/lib/CodeGen/PHIElimination.cpp
llvm/trunk/lib/CodeGen/PatchableFunction.cpp
llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp
llvm/trunk/lib/CodeGen/RegAllocFast.cpp
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
llvm/trunk/lib/CodeGen/SlotIndexes.cpp
llvm/trunk/lib/CodeGen/SplitKit.cpp
llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
llvm/trunk/lib/CodeGen/TailDuplicator.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
llvm/trunk/lib/CodeGen/TargetSchedule.cpp
llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp
llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.h
llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp
llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cpp
llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp
llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/trunk/lib/Target/ARC/ARCBranchFinalize.cpp
llvm/trunk/lib/Target/ARC/ARCInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMCallingConv.h
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/ARMMacroFusion.cpp
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
llvm/trunk/lib/Target/BPF/BPFInstrInfo.h
llvm/trunk/lib/Target/BPF/BPFRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h
llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h
llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp
llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSERegisterInfo.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h
llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h
llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp
llvm/trunk/lib/Target/X86/X86CallLowering.cpp
llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
llvm/trunk/lib/Target/X86/X86WinAllocaExpander.cpp
llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Tue Nov 7 17:01:31 2017
@@ -22,11 +22,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
Modified: llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h Tue Nov 7 17:01:31 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
Modified: llvm/trunk/include/llvm/CodeGen/TailDuplicator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TailDuplicator.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TailDuplicator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TailDuplicator.h Tue Nov 7 17:01:31 2017
@@ -17,12 +17,12 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
#include <vector>
Copied: llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h (from r317645, llvm/trunk/include/llvm/Target/TargetInstrInfo.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h?p2=llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h&p1=llvm/trunk/include/llvm/Target/TargetInstrInfo.h&r1=317645&r2=317647&rev=317647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -1,4 +1,4 @@
-//===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
+//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
Removed: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=317646&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h (removed)
@@ -1,1691 +0,0 @@
-//===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the target machine instruction set to the code generator.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETINSTRINFO_H
-#define LLVM_TARGET_TARGETINSTRINFO_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/DenseMapInfo.h"
-#include "llvm/ADT/None.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineCombinerPattern.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/Support/BranchProbability.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <cassert>
-#include <cstddef>
-#include <cstdint>
-#include <utility>
-#include <vector>
-
-namespace llvm {
-
-class DFAPacketizer;
-class InstrItineraryData;
-class LiveVariables;
-class MachineMemOperand;
-class MachineRegisterInfo;
-class MCAsmInfo;
-class MCInst;
-struct MCSchedModel;
-class Module;
-class ScheduleDAG;
-class ScheduleHazardRecognizer;
-class SDNode;
-class SelectionDAG;
-class RegScavenger;
-class TargetRegisterClass;
-class TargetRegisterInfo;
-class TargetSchedModel;
-class TargetSubtargetInfo;
-
-template <class T> class SmallVectorImpl;
-
-//---------------------------------------------------------------------------
-///
-/// TargetInstrInfo - Interface to description of machine instruction set
-///
-class TargetInstrInfo : public MCInstrInfo {
-public:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
- : CallFrameSetupOpcode(CFSetupOpcode),
- CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
- ReturnOpcode(ReturnOpcode) {}
- TargetInstrInfo(const TargetInstrInfo &) = delete;
- TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
- virtual ~TargetInstrInfo();
-
- static bool isGenericOpcode(unsigned Opc) {
- return Opc <= TargetOpcode::GENERIC_OP_END;
- }
-
- /// Given a machine instruction descriptor, returns the register
- /// class constraint for OpNum, or NULL.
- const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
- const TargetRegisterInfo *TRI,
- const MachineFunction &MF) const;
-
- /// Return true if the instruction is trivially rematerializable, meaning it
- /// has no side effects and requires no operands that aren't always available.
- /// This means the only allowed uses are constants and unallocatable physical
- /// registers so that the instructions result is independent of the place
- /// in the function.
- bool isTriviallyReMaterializable(const MachineInstr &MI,
- AliasAnalysis *AA = nullptr) const {
- return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
- (MI.getDesc().isRematerializable() &&
- (isReallyTriviallyReMaterializable(MI, AA) ||
- isReallyTriviallyReMaterializableGeneric(MI, AA)));
- }
-
-protected:
- /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
- /// set, this hook lets the target specify whether the instruction is actually
- /// trivially rematerializable, taking into consideration its operands. This
- /// predicate must return false if the instruction has any side effects other
- /// than producing a value, or if it requres any address registers that are
- /// not always available.
- /// Requirements must be check as stated in isTriviallyReMaterializable() .
- virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
- AliasAnalysis *AA) const {
- return false;
- }
-
- /// This method commutes the operands of the given machine instruction MI.
- /// The operands to be commuted are specified by their indices OpIdx1 and
- /// OpIdx2.
- ///
- /// If a target has any instructions that are commutable but require
- /// converting to different instructions or making non-trivial changes
- /// to commute them, this method can be overloaded to do that.
- /// The default implementation simply swaps the commutable operands.
- ///
- /// If NewMI is false, MI is modified in place and returned; otherwise, a
- /// new machine instruction is created and returned.
- ///
- /// Do not call this method for a non-commutable instruction.
- /// Even though the instruction is commutable, the method may still
- /// fail to commute the operands, null pointer is returned in such cases.
- virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
- unsigned OpIdx1,
- unsigned OpIdx2) const;
-
- /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
- /// operand indices to (ResultIdx1, ResultIdx2).
- /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
- /// predefined to some indices or be undefined (designated by the special
- /// value 'CommuteAnyOperandIndex').
- /// The predefined result indices cannot be re-defined.
- /// The function returns true iff after the result pair redefinition
- /// the fixed result pair is equal to or equivalent to the source pair of
- /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
- /// the pairs (x,y) and (y,x) are equivalent.
- static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
- unsigned CommutableOpIdx1,
- unsigned CommutableOpIdx2);
-
-private:
- /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
- /// set and the target hook isReallyTriviallyReMaterializable returns false,
- /// this function does target-independent tests to determine if the
- /// instruction is really trivially rematerializable.
- bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
- AliasAnalysis *AA) const;
-
-public:
- /// These methods return the opcode of the frame setup/destroy instructions
- /// if they exist (-1 otherwise). Some targets use pseudo instructions in
- /// order to abstract away the difference between operating with a frame
- /// pointer and operating without, through the use of these two instructions.
- ///
- unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
- unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
-
- /// Returns true if the argument is a frame pseudo instruction.
- bool isFrameInstr(const MachineInstr &I) const {
- return I.getOpcode() == getCallFrameSetupOpcode() ||
- I.getOpcode() == getCallFrameDestroyOpcode();
- }
-
- /// Returns true if the argument is a frame setup pseudo instruction.
- bool isFrameSetup(const MachineInstr &I) const {
- return I.getOpcode() == getCallFrameSetupOpcode();
- }
-
- /// Returns size of the frame associated with the given frame instruction.
- /// For frame setup instruction this is frame that is set up space set up
- /// after the instruction. For frame destroy instruction this is the frame
- /// freed by the caller.
- /// Note, in some cases a call frame (or a part of it) may be prepared prior
- /// to the frame setup instruction. It occurs in the calls that involve
- /// inalloca arguments. This function reports only the size of the frame part
- /// that is set up between the frame setup and destroy pseudo instructions.
- int64_t getFrameSize(const MachineInstr &I) const {
- assert(isFrameInstr(I) && "Not a frame instruction");
- assert(I.getOperand(0).getImm() >= 0);
- return I.getOperand(0).getImm();
- }
-
- /// Returns the total frame size, which is made up of the space set up inside
- /// the pair of frame start-stop instructions and the space that is set up
- /// prior to the pair.
- int64_t getFrameTotalSize(const MachineInstr &I) const {
- if (isFrameSetup(I)) {
- assert(I.getOperand(1).getImm() >= 0 &&
- "Frame size must not be negative");
- return getFrameSize(I) + I.getOperand(1).getImm();
- }
- return getFrameSize(I);
- }
-
- unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
- unsigned getReturnOpcode() const { return ReturnOpcode; }
-
- /// Returns the actual stack pointer adjustment made by an instruction
- /// as part of a call sequence. By default, only call frame setup/destroy
- /// instructions adjust the stack, but targets may want to override this
- /// to enable more fine-grained adjustment, or adjust by a different value.
- virtual int getSPAdjust(const MachineInstr &MI) const;
-
- /// Return true if the instruction is a "coalescable" extension instruction.
- /// That is, it's like a copy where it's legal for the source to overlap the
- /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
- /// expected the pre-extension value is available as a subreg of the result
- /// register. This also returns the sub-register index in SubIdx.
- virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
- unsigned &DstReg, unsigned &SubIdx) const {
- return false;
- }
-
- /// If the specified machine instruction is a direct
- /// load from a stack slot, return the virtual or physical register number of
- /// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than loading from the stack slot.
- virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- return 0;
- }
-
- /// Check for post-frame ptr elimination stack locations as well.
- /// This uses a heuristic so it isn't reliable for correctness.
- virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
- int &FrameIndex) const {
- return 0;
- }
-
- /// If the specified machine instruction has a load from a stack slot,
- /// return true along with the FrameIndex of the loaded stack slot and the
- /// machine mem operand containing the reference.
- /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
- /// any instructions that loads from the stack. This is just a hint, as some
- /// cases may be missed.
- virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const;
-
- /// If the specified machine instruction is a direct
- /// store to a stack slot, return the virtual or physical register number of
- /// the source reg along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than storing to the stack slot.
- virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- return 0;
- }
-
- /// Check for post-frame ptr elimination stack locations as well.
- /// This uses a heuristic, so it isn't reliable for correctness.
- virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
- int &FrameIndex) const {
- return 0;
- }
-
- /// If the specified machine instruction has a store to a stack slot,
- /// return true along with the FrameIndex of the loaded stack slot and the
- /// machine mem operand containing the reference.
- /// If not, return false. Unlike isStoreToStackSlot,
- /// this returns true for any instructions that stores to the
- /// stack. This is just a hint, as some cases may be missed.
- virtual bool hasStoreToStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const;
-
- /// Return true if the specified machine instruction
- /// is a copy of one stack slot to another and has no other effect.
- /// Provide the identity of the two frame indices.
- virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
- int &SrcFrameIndex) const {
- return false;
- }
-
- /// Compute the size in bytes and offset within a stack slot of a spilled
- /// register or subregister.
- ///
- /// \param [out] Size in bytes of the spilled value.
- /// \param [out] Offset in bytes within the stack slot.
- /// \returns true if both Size and Offset are successfully computed.
- ///
- /// Not all subregisters have computable spill slots. For example,
- /// subregisters registers may not be byte-sized, and a pair of discontiguous
- /// subregisters has no single offset.
- ///
- /// Targets with nontrivial bigendian implementations may need to override
- /// this, particularly to support spilled vector registers.
- virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
- unsigned &Size, unsigned &Offset,
- const MachineFunction &MF) const;
-
- /// Returns the size in bytes of the specified MachineInstr, or ~0U
- /// when this function is not implemented by a target.
- virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
- return ~0U;
- }
-
- /// Return true if the instruction is as cheap as a move instruction.
- ///
- /// Targets for different archs need to override this, and different
- /// micro-architectures can also be finely tuned inside.
- virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
- return MI.isAsCheapAsAMove();
- }
-
- /// Return true if the instruction should be sunk by MachineSink.
- ///
- /// MachineSink determines on its own whether the instruction is safe to sink;
- /// this gives the target a hook to override the default behavior with regards
- /// to which instructions should be sunk.
- virtual bool shouldSink(const MachineInstr &MI) const { return true; }
-
- /// Re-issue the specified 'original' instruction at the
- /// specific location targeting a new destination register.
- /// The register in Orig->getOperand(0).getReg() will be substituted by
- /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
- /// SubIdx.
- virtual void reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, unsigned DestReg,
- unsigned SubIdx, const MachineInstr &Orig,
- const TargetRegisterInfo &TRI) const;
-
- /// \brief Clones instruction or the whole instruction bundle \p Orig and
- /// insert into \p MBB before \p InsertBefore. The target may update operands
- /// that are required to be unique.
- ///
- /// \p Orig must not return true for MachineInstr::isNotDuplicable().
- virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator InsertBefore,
- const MachineInstr &Orig) const;
-
- /// This method must be implemented by targets that
- /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
- /// may be able to convert a two-address instruction into one or more true
- /// three-address instructions on demand. This allows the X86 target (for
- /// example) to convert ADD and SHL instructions into LEA instructions if they
- /// would require register copies due to two-addressness.
- ///
- /// This method returns a null pointer if the transformation cannot be
- /// performed, otherwise it returns the last new instruction.
- ///
- virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
- MachineInstr &MI,
- LiveVariables *LV) const {
- return nullptr;
- }
-
- // This constant can be used as an input value of operand index passed to
- // the method findCommutedOpIndices() to tell the method that the
- // corresponding operand index is not pre-defined and that the method
- // can pick any commutable operand.
- static const unsigned CommuteAnyOperandIndex = ~0U;
-
- /// This method commutes the operands of the given machine instruction MI.
- ///
- /// The operands to be commuted are specified by their indices OpIdx1 and
- /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
- /// 'CommuteAnyOperandIndex', which means that the method is free to choose
- /// any arbitrarily chosen commutable operand. If both arguments are set to
- /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
- /// operands; then commutes them if such operands could be found.
- ///
- /// If NewMI is false, MI is modified in place and returned; otherwise, a
- /// new machine instruction is created and returned.
- ///
- /// Do not call this method for a non-commutable instruction or
- /// for non-commuable operands.
- /// Even though the instruction is commutable, the method may still
- /// fail to commute the operands, null pointer is returned in such cases.
- MachineInstr *
- commuteInstruction(MachineInstr &MI, bool NewMI = false,
- unsigned OpIdx1 = CommuteAnyOperandIndex,
- unsigned OpIdx2 = CommuteAnyOperandIndex) const;
-
- /// Returns true iff the routine could find two commutable operands in the
- /// given machine instruction.
- /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
- /// If any of the INPUT values is set to the special value
- /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
- /// operand, then returns its index in the corresponding argument.
- /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
- /// looks for 2 commutable operands.
- /// If INPUT values refer to some operands of MI, then the method simply
- /// returns true if the corresponding operands are commutable and returns
- /// false otherwise.
- ///
- /// For example, calling this method this way:
- /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
- /// findCommutedOpIndices(MI, Op1, Op2);
- /// can be interpreted as a query asking to find an operand that would be
- /// commutable with the operand#1.
- virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
- unsigned &SrcOpIdx2) const;
-
- /// A pair composed of a register and a sub-register index.
- /// Used to give some type checking when modeling Reg:SubReg.
- struct RegSubRegPair {
- unsigned Reg;
- unsigned SubReg;
-
- RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
- : Reg(Reg), SubReg(SubReg) {}
- };
-
- /// A pair composed of a pair of a register and a sub-register index,
- /// and another sub-register index.
- /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
- struct RegSubRegPairAndIdx : RegSubRegPair {
- unsigned SubIdx;
-
- RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
- unsigned SubIdx = 0)
- : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
- };
-
- /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
- /// and \p DefIdx.
- /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
- /// the list is modeled as <Reg:SubReg, SubIdx>.
- /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
- /// two elements:
- /// - vreg1:sub1, sub0
- /// - vreg2<:0>, sub1
- ///
- /// \returns true if it is possible to build such an input sequence
- /// with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
- ///
- /// \note The generic implementation does not provide any support for
- /// MI.isRegSequenceLike(). In other words, one has to override
- /// getRegSequenceLikeInputs for target specific instructions.
- bool
- getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
- SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
-
- /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
- /// and \p DefIdx.
- /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
- /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
- /// - vreg1:sub1, sub0
- ///
- /// \returns true if it is possible to build such an input sequence
- /// with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
- ///
- /// \note The generic implementation does not provide any support for
- /// MI.isExtractSubregLike(). In other words, one has to override
- /// getExtractSubregLikeInputs for target specific instructions.
- bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPairAndIdx &InputReg) const;
-
- /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
- /// and \p DefIdx.
- /// \p [out] BaseReg and \p [out] InsertedReg contain
- /// the equivalent inputs of INSERT_SUBREG.
- /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
- /// - BaseReg: vreg0:sub0
- /// - InsertedReg: vreg1:sub1, sub3
- ///
- /// \returns true if it is possible to build such an input sequence
- /// with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
- ///
- /// \note The generic implementation does not provide any support for
- /// MI.isInsertSubregLike(). In other words, one has to override
- /// getInsertSubregLikeInputs for target specific instructions.
- bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPair &BaseReg,
- RegSubRegPairAndIdx &InsertedReg) const;
-
- /// Return true if two machine instructions would produce identical values.
- /// By default, this is only true when the two instructions
- /// are deemed identical except for defs. If this function is called when the
- /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
- /// aggressive checks.
- virtual bool produceSameValue(const MachineInstr &MI0,
- const MachineInstr &MI1,
- const MachineRegisterInfo *MRI = nullptr) const;
-
- /// \returns true if a branch from an instruction with opcode \p BranchOpc
- /// bytes is capable of jumping to a position \p BrOffset bytes away.
- virtual bool isBranchOffsetInRange(unsigned BranchOpc,
- int64_t BrOffset) const {
- llvm_unreachable("target did not implement");
- }
-
- /// \returns The block that branch instruction \p MI jumps to.
- virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
- llvm_unreachable("target did not implement");
- }
-
- /// Insert an unconditional indirect branch at the end of \p MBB to \p
- /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
- /// the offset of the position to insert the new branch.
- ///
- /// \returns The number of bytes added to the block.
- virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
- MachineBasicBlock &NewDestBB,
- const DebugLoc &DL,
- int64_t BrOffset = 0,
- RegScavenger *RS = nullptr) const {
- llvm_unreachable("target did not implement");
- }
-
- /// Analyze the branching code at the end of MBB, returning
- /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
- /// implemented for a target). Upon success, this returns false and returns
- /// with the following information in various cases:
- ///
- /// 1. If this block ends with no branches (it just falls through to its succ)
- /// just return false, leaving TBB/FBB null.
- /// 2. If this block ends with only an unconditional branch, it sets TBB to be
- /// the destination block.
- /// 3. If this block ends with a conditional branch and it falls through to a
- /// successor block, it sets TBB to be the branch destination block and a
- /// list of operands that evaluate the condition. These operands can be
- /// passed to other TargetInstrInfo methods to create new branches.
- /// 4. If this block ends with a conditional branch followed by an
- /// unconditional branch, it returns the 'true' destination in TBB, the
- /// 'false' destination in FBB, and a list of operands that evaluate the
- /// condition. These operands can be passed to other TargetInstrInfo
- /// methods to create new branches.
- ///
- /// Note that removeBranch and insertBranch must be implemented to support
- /// cases where this method returns success.
- ///
- /// If AllowModify is true, then this routine is allowed to modify the basic
- /// block (e.g. delete instructions after the unconditional branch).
- ///
- /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
- /// before calling this function.
- virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
- MachineBasicBlock *&FBB,
- SmallVectorImpl<MachineOperand> &Cond,
- bool AllowModify = false) const {
- return true;
- }
-
- /// Represents a predicate at the MachineFunction level. The control flow a
- /// MachineBranchPredicate represents is:
- ///
- /// Reg <def>= LHS `Predicate` RHS == ConditionDef
- /// if Reg then goto TrueDest else goto FalseDest
- ///
- struct MachineBranchPredicate {
- enum ComparePredicate {
- PRED_EQ, // True if two values are equal
- PRED_NE, // True if two values are not equal
- PRED_INVALID // Sentinel value
- };
-
- ComparePredicate Predicate = PRED_INVALID;
- MachineOperand LHS = MachineOperand::CreateImm(0);
- MachineOperand RHS = MachineOperand::CreateImm(0);
- MachineBasicBlock *TrueDest = nullptr;
- MachineBasicBlock *FalseDest = nullptr;
- MachineInstr *ConditionDef = nullptr;
-
- /// SingleUseCondition is true if ConditionDef is dead except for the
- /// branch(es) at the end of the basic block.
- ///
- bool SingleUseCondition = false;
-
- explicit MachineBranchPredicate() = default;
- };
-
- /// Analyze the branching code at the end of MBB and parse it into the
- /// MachineBranchPredicate structure if possible. Returns false on success
- /// and true on failure.
- ///
- /// If AllowModify is true, then this routine is allowed to modify the basic
- /// block (e.g. delete instructions after the unconditional branch).
- ///
- virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
- MachineBranchPredicate &MBP,
- bool AllowModify = false) const {
- return true;
- }
-
- /// Remove the branching code at the end of the specific MBB.
- /// This is only invoked in cases where AnalyzeBranch returns success. It
- /// returns the number of instructions that were removed.
- /// If \p BytesRemoved is non-null, report the change in code size from the
- /// removed instructions.
- virtual unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const {
- llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
- }
-
- /// Insert branch code into the end of the specified MachineBasicBlock. The
- /// operands to this method are the same as those returned by AnalyzeBranch.
- /// This is only invoked in cases where AnalyzeBranch returns success. It
- /// returns the number of instructions inserted. If \p BytesAdded is non-null,
- /// report the change in code size from the added instructions.
- ///
- /// It is also invoked by tail merging to add unconditional branches in
- /// cases where AnalyzeBranch doesn't apply because there was no original
- /// branch to analyze. At least this much must be implemented, else tail
- /// merging needs to be disabled.
- ///
- /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
- /// before calling this function.
- virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const {
- llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
- }
-
- unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *DestBB,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const {
- return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
- BytesAdded);
- }
-
- /// Analyze the loop code, return true if it cannot be understoo. Upon
- /// success, this function returns false and returns information about the
- /// induction variable and compare instruction used at the end.
- virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
- MachineInstr *&CmpInst) const {
- return true;
- }
-
- /// Generate code to reduce the loop iteration by one and check if the loop is
- /// finished. Return the value/register of the the new loop count. We need
- /// this function when peeling off one or more iterations of a loop. This
- /// function assumes the nth iteration is peeled first.
- virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
- MachineInstr &Cmp,
- SmallVectorImpl<MachineOperand> &Cond,
- SmallVectorImpl<MachineInstr *> &PrevInsts,
- unsigned Iter, unsigned MaxIter) const {
- llvm_unreachable("Target didn't implement ReduceLoopCount");
- }
-
- /// Delete the instruction OldInst and everything after it, replacing it with
- /// an unconditional branch to NewDest. This is used by the tail merging pass.
- virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
- MachineBasicBlock *NewDest) const;
-
- /// Return true if it's legal to split the given basic
- /// block at the specified instruction (i.e. instruction would be the start
- /// of a new basic block).
- virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI) const {
- return true;
- }
-
- /// Return true if it's profitable to predicate
- /// instructions with accumulated instruction latency of "NumCycles"
- /// of the specified basic block, where the probability of the instructions
- /// being executed is given by Probability, and Confidence is a measure
- /// of our confidence that it will be properly predicted.
- virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
- unsigned ExtraPredCycles,
- BranchProbability Probability) const {
- return false;
- }
-
- /// Second variant of isProfitableToIfCvt. This one
- /// checks for the case where two basic blocks from true and false path
- /// of a if-then-else (diamond) are predicated on mutally exclusive
- /// predicates, where the probability of the true path being taken is given
- /// by Probability, and Confidence is a measure of our confidence that it
- /// will be properly predicted.
- virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
- unsigned ExtraTCycles,
- MachineBasicBlock &FMBB, unsigned NumFCycles,
- unsigned ExtraFCycles,
- BranchProbability Probability) const {
- return false;
- }
-
- /// Return true if it's profitable for if-converter to duplicate instructions
- /// of specified accumulated instruction latencies in the specified MBB to
- /// enable if-conversion.
- /// The probability of the instructions being executed is given by
- /// Probability, and Confidence is a measure of our confidence that it
- /// will be properly predicted.
- virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
- unsigned NumCycles,
- BranchProbability Probability) const {
- return false;
- }
-
- /// Return true if it's profitable to unpredicate
- /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
- /// exclusive predicates.
- /// e.g.
- /// subeq r0, r1, #1
- /// addne r0, r1, #1
- /// =>
- /// sub r0, r1, #1
- /// addne r0, r1, #1
- ///
- /// This may be profitable is conditional instructions are always executed.
- virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
- MachineBasicBlock &FMBB) const {
- return false;
- }
-
- /// Return true if it is possible to insert a select
- /// instruction that chooses between TrueReg and FalseReg based on the
- /// condition code in Cond.
- ///
- /// When successful, also return the latency in cycles from TrueReg,
- /// FalseReg, and Cond to the destination register. In most cases, a select
- /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
- ///
- /// Some x86 implementations have 2-cycle cmov instructions.
- ///
- /// @param MBB Block where select instruction would be inserted.
- /// @param Cond Condition returned by AnalyzeBranch.
- /// @param TrueReg Virtual register to select when Cond is true.
- /// @param FalseReg Virtual register to select when Cond is false.
- /// @param CondCycles Latency from Cond+Branch to select output.
- /// @param TrueCycles Latency from TrueReg to select output.
- /// @param FalseCycles Latency from FalseReg to select output.
- virtual bool canInsertSelect(const MachineBasicBlock &MBB,
- ArrayRef<MachineOperand> Cond, unsigned TrueReg,
- unsigned FalseReg, int &CondCycles,
- int &TrueCycles, int &FalseCycles) const {
- return false;
- }
-
- /// Insert a select instruction into MBB before I that will copy TrueReg to
- /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
- ///
- /// This function can only be called after canInsertSelect() returned true.
- /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
- /// that the same flags or registers required by Cond are available at the
- /// insertion point.
- ///
- /// @param MBB Block where select instruction should be inserted.
- /// @param I Insertion point.
- /// @param DL Source location for debugging.
- /// @param DstReg Virtual register to be defined by select instruction.
- /// @param Cond Condition as computed by AnalyzeBranch.
- /// @param TrueReg Virtual register to copy when Cond is true.
- /// @param FalseReg Virtual register to copy when Cons is false.
- virtual void insertSelect(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I, const DebugLoc &DL,
- unsigned DstReg, ArrayRef<MachineOperand> Cond,
- unsigned TrueReg, unsigned FalseReg) const {
- llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
- }
-
- /// Analyze the given select instruction, returning true if
- /// it cannot be understood. It is assumed that MI->isSelect() is true.
- ///
- /// When successful, return the controlling condition and the operands that
- /// determine the true and false result values.
- ///
- /// Result = SELECT Cond, TrueOp, FalseOp
- ///
- /// Some targets can optimize select instructions, for example by predicating
- /// the instruction defining one of the operands. Such targets should set
- /// Optimizable.
- ///
- /// @param MI Select instruction to analyze.
- /// @param Cond Condition controlling the select.
- /// @param TrueOp Operand number of the value selected when Cond is true.
- /// @param FalseOp Operand number of the value selected when Cond is false.
- /// @param Optimizable Returned as true if MI is optimizable.
- /// @returns False on success.
- virtual bool analyzeSelect(const MachineInstr &MI,
- SmallVectorImpl<MachineOperand> &Cond,
- unsigned &TrueOp, unsigned &FalseOp,
- bool &Optimizable) const {
- assert(MI.getDesc().isSelect() && "MI must be a select instruction");
- return true;
- }
-
- /// Given a select instruction that was understood by
- /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
- /// merging it with one of its operands. Returns NULL on failure.
- ///
- /// When successful, returns the new select instruction. The client is
- /// responsible for deleting MI.
- ///
- /// If both sides of the select can be optimized, PreferFalse is used to pick
- /// a side.
- ///
- /// @param MI Optimizable select instruction.
- /// @param NewMIs Set that record all MIs in the basic block up to \p
- /// MI. Has to be updated with any newly created MI or deleted ones.
- /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
- /// @returns Optimized instruction or NULL.
- virtual MachineInstr *optimizeSelect(MachineInstr &MI,
- SmallPtrSetImpl<MachineInstr *> &NewMIs,
- bool PreferFalse = false) const {
- // This function must be implemented if Optimizable is ever set.
- llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
- }
-
- /// Emit instructions to copy a pair of physical registers.
- ///
- /// This function should support copies within any legal register class as
- /// well as any cross-class copies created during instruction selection.
- ///
- /// The source and destination registers may overlap, which may require a
- /// careful implementation when multiple copy instructions are required for
- /// large registers. See for example the ARM target.
- virtual void copyPhysReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, const DebugLoc &DL,
- unsigned DestReg, unsigned SrcReg,
- bool KillSrc) const {
- llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
- }
-
- /// Store the specified register of the given register class to the specified
- /// stack frame index. The store instruction is to be added to the given
- /// machine basic block before the specified machine instruction. If isKill
- /// is true, the register operand is the last use and must be marked kill.
- virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI) const {
- llvm_unreachable("Target didn't implement "
- "TargetInstrInfo::storeRegToStackSlot!");
- }
-
- /// Load the specified register of the given register class from the specified
- /// stack frame index. The load instruction is to be added to the given
- /// machine basic block before the specified machine instruction.
- virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI) const {
- llvm_unreachable("Target didn't implement "
- "TargetInstrInfo::loadRegFromStackSlot!");
- }
-
- /// This function is called for all pseudo instructions
- /// that remain after register allocation. Many pseudo instructions are
- /// created to help register allocation. This is the place to convert them
- /// into real instructions. The target can edit MI in place, or it can insert
- /// new instructions and erase MI. The function should return true if
- /// anything was changed.
- virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
-
- /// Check whether the target can fold a load that feeds a subreg operand
- /// (or a subreg operand that feeds a store).
- /// For example, X86 may want to return true if it can fold
- /// movl (%esp), %eax
- /// subb, %al, ...
- /// Into:
- /// subb (%esp), ...
- ///
- /// Ideally, we'd like the target implementation of foldMemoryOperand() to
- /// reject subregs - but since this behavior used to be enforced in the
- /// target-independent code, moving this responsibility to the targets
- /// has the potential of causing nasty silent breakage in out-of-tree targets.
- virtual bool isSubregFoldable() const { return false; }
-
- /// Attempt to fold a load or store of the specified stack
- /// slot into the specified machine instruction for the specified operand(s).
- /// If this is possible, a new instruction is returned with the specified
- /// operand folded, otherwise NULL is returned.
- /// The new instruction is inserted before MI, and the client is responsible
- /// for removing the old instruction.
- MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
- int FrameIndex,
- LiveIntervals *LIS = nullptr) const;
-
- /// Same as the previous version except it allows folding of any load and
- /// store from / to any address, not just from a specific stack slot.
- MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
- MachineInstr &LoadMI,
- LiveIntervals *LIS = nullptr) const;
-
- /// Return true when there is potentially a faster code sequence
- /// for an instruction chain ending in \p Root. All potential patterns are
- /// returned in the \p Pattern vector. Pattern should be sorted in priority
- /// order since the pattern evaluator stops checking as soon as it finds a
- /// faster sequence.
- /// \param Root - Instruction that could be combined with one of its operands
- /// \param Patterns - Vector of possible combination patterns
- virtual bool getMachineCombinerPatterns(
- MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
-
- /// Return true when a code sequence can improve throughput. It
- /// should be called only for instructions in loops.
- /// \param Pattern - combiner pattern
- virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
-
- /// Return true if the input \P Inst is part of a chain of dependent ops
- /// that are suitable for reassociation, otherwise return false.
- /// If the instruction's operands must be commuted to have a previous
- /// instruction of the same type define the first source operand, \P Commuted
- /// will be set to true.
- bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
-
- /// Return true when \P Inst is both associative and commutative.
- virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
- return false;
- }
-
- /// Return true when \P Inst has reassociable operands in the same \P MBB.
- virtual bool hasReassociableOperands(const MachineInstr &Inst,
- const MachineBasicBlock *MBB) const;
-
- /// Return true when \P Inst has reassociable sibling.
- bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
-
- /// When getMachineCombinerPatterns() finds patterns, this function generates
- /// the instructions that could replace the original code sequence. The client
- /// has to decide whether the actual replacement is beneficial or not.
- /// \param Root - Instruction that could be combined with one of its operands
- /// \param Pattern - Combination pattern for Root
- /// \param InsInstrs - Vector of new instructions that implement P
- /// \param DelInstrs - Old instructions, including Root, that could be
- /// replaced by InsInstr
- /// \param InstrIdxForVirtReg - map of virtual register to instruction in
- /// InsInstr that defines it
- virtual void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
-
- /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
- /// reduce critical path length.
- void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
-
- /// This is an architecture-specific helper function of reassociateOps.
- /// Set special operand attributes for new instructions after reassociation.
- virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
- MachineInstr &NewMI1,
- MachineInstr &NewMI2) const {}
-
- /// Return true when a target supports MachineCombiner.
- virtual bool useMachineCombiner() const { return false; }
-
-protected:
- /// Target-dependent implementation for foldMemoryOperand.
- /// Target-independent code in foldMemoryOperand will
- /// take care of adding a MachineMemOperand to the newly created instruction.
- /// The instruction and any auxiliary instructions necessary will be inserted
- /// at InsertPt.
- virtual MachineInstr *
- foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
- ArrayRef<unsigned> Ops,
- MachineBasicBlock::iterator InsertPt, int FrameIndex,
- LiveIntervals *LIS = nullptr) const {
- return nullptr;
- }
-
- /// Target-dependent implementation for foldMemoryOperand.
- /// Target-independent code in foldMemoryOperand will
- /// take care of adding a MachineMemOperand to the newly created instruction.
- /// The instruction and any auxiliary instructions necessary will be inserted
- /// at InsertPt.
- virtual MachineInstr *foldMemoryOperandImpl(
- MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
- MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
- LiveIntervals *LIS = nullptr) const {
- return nullptr;
- }
-
- /// \brief Target-dependent implementation of getRegSequenceInputs.
- ///
- /// \returns true if it is possible to build the equivalent
- /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isRegSequenceLike().
- ///
- /// \see TargetInstrInfo::getRegSequenceInputs.
- virtual bool getRegSequenceLikeInputs(
- const MachineInstr &MI, unsigned DefIdx,
- SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
- return false;
- }
-
- /// \brief Target-dependent implementation of getExtractSubregInputs.
- ///
- /// \returns true if it is possible to build the equivalent
- /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isExtractSubregLike().
- ///
- /// \see TargetInstrInfo::getExtractSubregInputs.
- virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
- unsigned DefIdx,
- RegSubRegPairAndIdx &InputReg) const {
- return false;
- }
-
- /// \brief Target-dependent implementation of getInsertSubregInputs.
- ///
- /// \returns true if it is possible to build the equivalent
- /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
- ///
- /// \pre MI.isInsertSubregLike().
- ///
- /// \see TargetInstrInfo::getInsertSubregInputs.
- virtual bool
- getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPair &BaseReg,
- RegSubRegPairAndIdx &InsertedReg) const {
- return false;
- }
-
-public:
- /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
- /// (e.g. stack) the target returns the corresponding address space.
- virtual unsigned
- getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
- return 0;
- }
-
- /// unfoldMemoryOperand - Separate a single instruction which folded a load or
- /// a store or a load and a store into two or more instruction. If this is
- /// possible, returns true as well as the new instructions by reference.
- virtual bool
- unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
- bool UnfoldLoad, bool UnfoldStore,
- SmallVectorImpl<MachineInstr *> &NewMIs) const {
- return false;
- }
-
- virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
- SmallVectorImpl<SDNode *> &NewNodes) const {
- return false;
- }
-
- /// Returns the opcode of the would be new
- /// instruction after load / store are unfolded from an instruction of the
- /// specified opcode. It returns zero if the specified unfolding is not
- /// possible. If LoadRegIndex is non-null, it is filled in with the operand
- /// index of the operand which will hold the register holding the loaded
- /// value.
- virtual unsigned
- getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
- unsigned *LoadRegIndex = nullptr) const {
- return 0;
- }
-
- /// This is used by the pre-regalloc scheduler to determine if two loads are
- /// loading from the same base address. It should only return true if the base
- /// pointers are the same and the only differences between the two addresses
- /// are the offset. It also returns the offsets by reference.
- virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
- int64_t &Offset1,
- int64_t &Offset2) const {
- return false;
- }
-
- /// This is a used by the pre-regalloc scheduler to determine (in conjunction
- /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
- /// On some targets if two loads are loading from
- /// addresses in the same cache line, it's better if they are scheduled
- /// together. This function takes two integers that represent the load offsets
- /// from the common base address. It returns true if it decides it's desirable
- /// to schedule the two loads together. "NumLoads" is the number of loads that
- /// have already been scheduled after Load1.
- virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
- int64_t Offset1, int64_t Offset2,
- unsigned NumLoads) const {
- return false;
- }
-
- /// Get the base register and byte offset of an instruction that reads/writes
- /// memory.
- virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
- int64_t &Offset,
- const TargetRegisterInfo *TRI) const {
- return false;
- }
-
- /// Return true if the instruction contains a base register and offset. If
- /// true, the function also sets the operand position in the instruction
- /// for the base register and offset.
- virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
- unsigned &BasePos,
- unsigned &OffsetPos) const {
- return false;
- }
-
- /// If the instruction is an increment of a constant value, return the amount.
- virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
- return false;
- }
-
- /// Returns true if the two given memory operations should be scheduled
- /// adjacent. Note that you have to add:
- /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
- /// or
- /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
- /// to TargetPassConfig::createMachineScheduler() to have an effect.
- virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
- MachineInstr &SecondLdSt, unsigned BaseReg2,
- unsigned NumLoads) const {
- llvm_unreachable("target did not implement shouldClusterMemOps()");
- }
-
- /// Reverses the branch condition of the specified condition list,
- /// returning false on success and true if it cannot be reversed.
- virtual bool
- reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
- return true;
- }
-
- /// Insert a noop into the instruction stream at the specified point.
- virtual void insertNoop(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const;
-
- /// Return the noop instruction to use for a noop.
- virtual void getNoop(MCInst &NopInst) const;
-
- /// Return true for post-incremented instructions.
- virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
-
- /// Returns true if the instruction is already predicated.
- virtual bool isPredicated(const MachineInstr &MI) const { return false; }
-
- /// Returns true if the instruction is a
- /// terminator instruction that has not been predicated.
- virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
-
- /// Returns true if MI is an unconditional tail call.
- virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
- return false;
- }
-
- /// Returns true if the tail call can be made conditional on BranchCond.
- virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
- const MachineInstr &TailCall) const {
- return false;
- }
-
- /// Replace the conditional branch in MBB with a conditional tail call.
- virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
- SmallVectorImpl<MachineOperand> &Cond,
- const MachineInstr &TailCall) const {
- llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
- }
-
- /// Convert the instruction into a predicated instruction.
- /// It returns true if the operation was successful.
- virtual bool PredicateInstruction(MachineInstr &MI,
- ArrayRef<MachineOperand> Pred) const;
-
- /// Returns true if the first specified predicate
- /// subsumes the second, e.g. GE subsumes GT.
- virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
- ArrayRef<MachineOperand> Pred2) const {
- return false;
- }
-
- /// If the specified instruction defines any predicate
- /// or condition code register(s) used for predication, returns true as well
- /// as the definition predicate(s) by reference.
- virtual bool DefinesPredicate(MachineInstr &MI,
- std::vector<MachineOperand> &Pred) const {
- return false;
- }
-
- /// Return true if the specified instruction can be predicated.
- /// By default, this returns true for every instruction with a
- /// PredicateOperand.
- virtual bool isPredicable(const MachineInstr &MI) const {
- return MI.getDesc().isPredicable();
- }
-
- /// Return true if it's safe to move a machine
- /// instruction that defines the specified register class.
- virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
- return true;
- }
-
- /// Test if the given instruction should be considered a scheduling boundary.
- /// This primarily includes labels and terminators.
- virtual bool isSchedulingBoundary(const MachineInstr &MI,
- const MachineBasicBlock *MBB,
- const MachineFunction &MF) const;
-
- /// Measure the specified inline asm to determine an approximation of its
- /// length.
- virtual unsigned getInlineAsmLength(const char *Str,
- const MCAsmInfo &MAI) const;
-
- /// Allocate and return a hazard recognizer to use for this target when
- /// scheduling the machine instructions before register allocation.
- virtual ScheduleHazardRecognizer *
- CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
- const ScheduleDAG *DAG) const;
-
- /// Allocate and return a hazard recognizer to use for this target when
- /// scheduling the machine instructions before register allocation.
- virtual ScheduleHazardRecognizer *
- CreateTargetMIHazardRecognizer(const InstrItineraryData *,
- const ScheduleDAG *DAG) const;
-
- /// Allocate and return a hazard recognizer to use for this target when
- /// scheduling the machine instructions after register allocation.
- virtual ScheduleHazardRecognizer *
- CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
- const ScheduleDAG *DAG) const;
-
- /// Allocate and return a hazard recognizer to use for by non-scheduling
- /// passes.
- virtual ScheduleHazardRecognizer *
- CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
- return nullptr;
- }
-
- /// Provide a global flag for disabling the PreRA hazard recognizer that
- /// targets may choose to honor.
- bool usePreRAHazardRecognizer() const;
-
- /// For a comparison instruction, return the source registers
- /// in SrcReg and SrcReg2 if having two register operands, and the value it
- /// compares against in CmpValue. Return true if the comparison instruction
- /// can be analyzed.
- virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
- unsigned &SrcReg2, int &Mask, int &Value) const {
- return false;
- }
-
- /// See if the comparison instruction can be converted
- /// into something more efficient. E.g., on ARM most instructions can set the
- /// flags register, obviating the need for a separate CMP.
- virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
- unsigned SrcReg2, int Mask, int Value,
- const MachineRegisterInfo *MRI) const {
- return false;
- }
- virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
-
- /// Try to remove the load by folding it to a register operand at the use.
- /// We fold the load instructions if and only if the
- /// def and use are in the same BB. We only look at one load and see
- /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
- /// defined by the load we are trying to fold. DefMI returns the machine
- /// instruction that defines FoldAsLoadDefReg, and the function returns
- /// the machine instruction generated due to folding.
- virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
- const MachineRegisterInfo *MRI,
- unsigned &FoldAsLoadDefReg,
- MachineInstr *&DefMI) const {
- return nullptr;
- }
-
- /// 'Reg' is known to be defined by a move immediate instruction,
- /// try to fold the immediate into the use instruction.
- /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
- /// then the caller may assume that DefMI has been erased from its parent
- /// block. The caller may assume that it will not be erased by this
- /// function otherwise.
- virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
- unsigned Reg, MachineRegisterInfo *MRI) const {
- return false;
- }
-
- /// Return the number of u-operations the given machine
- /// instruction will be decoded to on the target cpu. The itinerary's
- /// IssueWidth is the number of microops that can be dispatched each
- /// cycle. An instruction with zero microops takes no dispatch resources.
- virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
- const MachineInstr &MI) const;
-
- /// Return true for pseudo instructions that don't consume any
- /// machine resources in their current form. These are common cases that the
- /// scheduler should consider free, rather than conservatively handling them
- /// as instructions with no itinerary.
- bool isZeroCost(unsigned Opcode) const {
- return Opcode <= TargetOpcode::COPY;
- }
-
- virtual int getOperandLatency(const InstrItineraryData *ItinData,
- SDNode *DefNode, unsigned DefIdx,
- SDNode *UseNode, unsigned UseIdx) const;
-
- /// Compute and return the use operand latency of a given pair of def and use.
- /// In most cases, the static scheduling itinerary was enough to determine the
- /// operand latency. But it may not be possible for instructions with variable
- /// number of defs / uses.
- ///
- /// This is a raw interface to the itinerary that may be directly overridden
- /// by a target. Use computeOperandLatency to get the best estimate of
- /// latency.
- virtual int getOperandLatency(const InstrItineraryData *ItinData,
- const MachineInstr &DefMI, unsigned DefIdx,
- const MachineInstr &UseMI,
- unsigned UseIdx) const;
-
- /// Compute the instruction latency of a given instruction.
- /// If the instruction has higher cost when predicated, it's returned via
- /// PredCost.
- virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
- const MachineInstr &MI,
- unsigned *PredCost = nullptr) const;
-
- virtual unsigned getPredicationCost(const MachineInstr &MI) const;
-
- virtual int getInstrLatency(const InstrItineraryData *ItinData,
- SDNode *Node) const;
-
- /// Return the default expected latency for a def based on its opcode.
- unsigned defaultDefLatency(const MCSchedModel &SchedModel,
- const MachineInstr &DefMI) const;
-
- int computeDefOperandLatency(const InstrItineraryData *ItinData,
- const MachineInstr &DefMI) const;
-
- /// Return true if this opcode has high latency to its result.
- virtual bool isHighLatencyDef(int opc) const { return false; }
-
- /// Compute operand latency between a def of 'Reg'
- /// and a use in the current loop. Return true if the target considered
- /// it 'high'. This is used by optimization passes such as machine LICM to
- /// determine whether it makes sense to hoist an instruction out even in a
- /// high register pressure situation.
- virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
- const MachineRegisterInfo *MRI,
- const MachineInstr &DefMI, unsigned DefIdx,
- const MachineInstr &UseMI,
- unsigned UseIdx) const {
- return false;
- }
-
- /// Compute operand latency of a def of 'Reg'. Return true
- /// if the target considered it 'low'.
- virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
- const MachineInstr &DefMI,
- unsigned DefIdx) const;
-
- /// Perform target-specific instruction verification.
- virtual bool verifyInstruction(const MachineInstr &MI,
- StringRef &ErrInfo) const {
- return true;
- }
-
- /// Return the current execution domain and bit mask of
- /// possible domains for instruction.
- ///
- /// Some micro-architectures have multiple execution domains, and multiple
- /// opcodes that perform the same operation in different domains. For
- /// example, the x86 architecture provides the por, orps, and orpd
- /// instructions that all do the same thing. There is a latency penalty if a
- /// register is written in one domain and read in another.
- ///
- /// This function returns a pair (domain, mask) containing the execution
- /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
- /// function can be used to change the opcode to one of the domains in the
- /// bit mask. Instructions whose execution domain can't be changed should
- /// return a 0 mask.
- ///
- /// The execution domain numbers don't have any special meaning except domain
- /// 0 is used for instructions that are not associated with any interesting
- /// execution domain.
- ///
- virtual std::pair<uint16_t, uint16_t>
- getExecutionDomain(const MachineInstr &MI) const {
- return std::make_pair(0, 0);
- }
-
- /// Change the opcode of MI to execute in Domain.
- ///
- /// The bit (1 << Domain) must be set in the mask returned from
- /// getExecutionDomain(MI).
- virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
-
- /// Returns the preferred minimum clearance
- /// before an instruction with an unwanted partial register update.
- ///
- /// Some instructions only write part of a register, and implicitly need to
- /// read the other parts of the register. This may cause unwanted stalls
- /// preventing otherwise unrelated instructions from executing in parallel in
- /// an out-of-order CPU.
- ///
- /// For example, the x86 instruction cvtsi2ss writes its result to bits
- /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
- /// the instruction needs to wait for the old value of the register to become
- /// available:
- ///
- /// addps %xmm1, %xmm0
- /// movaps %xmm0, (%rax)
- /// cvtsi2ss %rbx, %xmm0
- ///
- /// In the code above, the cvtsi2ss instruction needs to wait for the addps
- /// instruction before it can issue, even though the high bits of %xmm0
- /// probably aren't needed.
- ///
- /// This hook returns the preferred clearance before MI, measured in
- /// instructions. Other defs of MI's operand OpNum are avoided in the last N
- /// instructions before MI. It should only return a positive value for
- /// unwanted dependencies. If the old bits of the defined register have
- /// useful values, or if MI is determined to otherwise read the dependency,
- /// the hook should return 0.
- ///
- /// The unwanted dependency may be handled by:
- ///
- /// 1. Allocating the same register for an MI def and use. That makes the
- /// unwanted dependency identical to a required dependency.
- ///
- /// 2. Allocating a register for the def that has no defs in the previous N
- /// instructions.
- ///
- /// 3. Calling breakPartialRegDependency() with the same arguments. This
- /// allows the target to insert a dependency breaking instruction.
- ///
- virtual unsigned
- getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
- // The default implementation returns 0 for no partial register dependency.
- return 0;
- }
-
- /// \brief Return the minimum clearance before an instruction that reads an
- /// unused register.
- ///
- /// For example, AVX instructions may copy part of a register operand into
- /// the unused high bits of the destination register.
- ///
- /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
- ///
- /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
- /// false dependence on any previous write to %xmm0.
- ///
- /// This hook works similarly to getPartialRegUpdateClearance, except that it
- /// does not take an operand index. Instead sets \p OpNum to the index of the
- /// unused register.
- virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
- const TargetRegisterInfo *TRI) const {
- // The default implementation returns 0 for no undef register dependency.
- return 0;
- }
-
- /// Insert a dependency-breaking instruction
- /// before MI to eliminate an unwanted dependency on OpNum.
- ///
- /// If it wasn't possible to avoid a def in the last N instructions before MI
- /// (see getPartialRegUpdateClearance), this hook will be called to break the
- /// unwanted dependency.
- ///
- /// On x86, an xorps instruction can be used as a dependency breaker:
- ///
- /// addps %xmm1, %xmm0
- /// movaps %xmm0, (%rax)
- /// xorps %xmm0, %xmm0
- /// cvtsi2ss %rbx, %xmm0
- ///
- /// An <imp-kill> operand should be added to MI if an instruction was
- /// inserted. This ties the instructions together in the post-ra scheduler.
- ///
- virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {}
-
- /// Create machine specific model for scheduling.
- virtual DFAPacketizer *
- CreateTargetScheduleState(const TargetSubtargetInfo &) const {
- return nullptr;
- }
-
- /// Sometimes, it is possible for the target
- /// to tell, even without aliasing information, that two MIs access different
- /// memory addresses. This function returns true if two MIs access different
- /// memory addresses and false otherwise.
- ///
- /// Assumes any physical registers used to compute addresses have the same
- /// value for both instructions. (This is the most useful assumption for
- /// post-RA scheduling.)
- ///
- /// See also MachineInstr::mayAlias, which is implemented on top of this
- /// function.
- virtual bool
- areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
- AliasAnalysis *AA = nullptr) const {
- assert((MIa.mayLoad() || MIa.mayStore()) &&
- "MIa must load from or modify a memory location");
- assert((MIb.mayLoad() || MIb.mayStore()) &&
- "MIb must load from or modify a memory location");
- return false;
- }
-
- /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
- /// which is a heuristic used for CSE'ing phys reg defs.
- virtual unsigned getMachineCSELookAheadLimit() const {
- // The default lookahead is small to prevent unprofitable quadratic
- // behavior.
- return 5;
- }
-
- /// Return an array that contains the ids of the target indices (used for the
- /// TargetIndex machine operand) and their names.
- ///
- /// MIR Serialization is able to serialize only the target indices that are
- /// defined by this method.
- virtual ArrayRef<std::pair<int, const char *>>
- getSerializableTargetIndices() const {
- return None;
- }
-
- /// Decompose the machine operand's target flags into two values - the direct
- /// target flag value and any of bit flags that are applied.
- virtual std::pair<unsigned, unsigned>
- decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
- return std::make_pair(0u, 0u);
- }
-
- /// Return an array that contains the direct target flag values and their
- /// names.
- ///
- /// MIR Serialization is able to serialize only the target flags that are
- /// defined by this method.
- virtual ArrayRef<std::pair<unsigned, const char *>>
- getSerializableDirectMachineOperandTargetFlags() const {
- return None;
- }
-
- /// Return an array that contains the bitmask target flag values and their
- /// names.
- ///
- /// MIR Serialization is able to serialize only the target flags that are
- /// defined by this method.
- virtual ArrayRef<std::pair<unsigned, const char *>>
- getSerializableBitmaskMachineOperandTargetFlags() const {
- return None;
- }
-
- /// Return an array that contains the MMO target flag values and their
- /// names.
- ///
- /// MIR Serialization is able to serialize only the MMO target flags that are
- /// defined by this method.
- virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
- getSerializableMachineMemOperandTargetFlags() const {
- return None;
- }
-
- /// Determines whether \p Inst is a tail call instruction. Override this
- /// method on targets that do not properly set MCID::Return and MCID::Call on
- /// tail call instructions."
- virtual bool isTailCall(const MachineInstr &Inst) const {
- return Inst.isReturn() && Inst.isCall();
- }
-
- /// True if the instruction is bound to the top of its basic block and no
- /// other instructions shall be inserted before it. This can be implemented
- /// to prevent register allocator to insert spills before such instructions.
- virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
- return false;
- }
-
- /// \brief Describes the number of instructions that it will take to call and
- /// construct a frame for a given outlining candidate.
- struct MachineOutlinerInfo {
- /// Number of instructions to call an outlined function for this candidate.
- unsigned CallOverhead;
-
- /// \brief Number of instructions to construct an outlined function frame
- /// for this candidate.
- unsigned FrameOverhead;
-
- /// \brief Represents the specific instructions that must be emitted to
- /// construct a call to this candidate.
- unsigned CallConstructionID;
-
- /// \brief Represents the specific instructions that must be emitted to
- /// construct a frame for this candidate's outlined function.
- unsigned FrameConstructionID;
-
- MachineOutlinerInfo() {}
- MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
- unsigned CallConstructionID,
- unsigned FrameConstructionID)
- : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
- CallConstructionID(CallConstructionID),
- FrameConstructionID(FrameConstructionID) {}
- };
-
- /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
- /// information for a set of outlining candidates.
- virtual MachineOutlinerInfo getOutlininingCandidateInfo(
- std::vector<
- std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
- &RepeatedSequenceLocs) const {
- llvm_unreachable(
- "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
- }
-
- /// Represents how an instruction should be mapped by the outliner.
- /// \p Legal instructions are those which are safe to outline.
- /// \p Illegal instructions are those which cannot be outlined.
- /// \p Invisible instructions are instructions which can be outlined, but
- /// shouldn't actually impact the outlining result.
- enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
-
- /// Returns how or if \p MI should be outlined.
- virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
- llvm_unreachable(
- "Target didn't implement TargetInstrInfo::getOutliningType!");
- }
-
- /// Insert a custom epilogue for outlined functions.
- /// This may be empty, in which case no epilogue or return statement will be
- /// emitted.
- virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
- MachineFunction &MF,
- const MachineOutlinerInfo &MInfo) const {
- llvm_unreachable(
- "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
- }
-
- /// Insert a call to an outlined function into the program.
- /// Returns an iterator to the spot where we inserted the call. This must be
- /// implemented by the target.
- virtual MachineBasicBlock::iterator
- insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &It, MachineFunction &MF,
- const MachineOutlinerInfo &MInfo) const {
- llvm_unreachable(
- "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
- }
-
- /// Insert a custom prologue for outlined functions.
- /// This may be empty, in which case no prologue will be emitted.
- virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
- MachineFunction &MF,
- const MachineOutlinerInfo &MInfo) const {
- llvm_unreachable(
- "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
- }
-
- /// Return true if the function can safely be outlined from.
- /// A function \p MF is considered safe for outlining if an outlined function
- /// produced from instructions in F will produce a program which produces the
- /// same output for any set of given inputs.
- virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
- bool OutlineFromLinkOnceODRs) const {
- llvm_unreachable("Target didn't implement "
- "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
- }
-
-private:
- unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
- unsigned CatchRetOpcode;
- unsigned ReturnOpcode;
-};
-
-/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
-template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
- using RegInfo = DenseMapInfo<unsigned>;
-
- static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
- return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
- RegInfo::getEmptyKey());
- }
-
- static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
- return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
- RegInfo::getTombstoneKey());
- }
-
- /// \brief Reuse getHashValue implementation from
- /// std::pair<unsigned, unsigned>.
- static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
- std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
- return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
- }
-
- static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
- const TargetInstrInfo::RegSubRegPair &RHS) {
- return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
- RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
- }
-};
-
-} // end namespace llvm
-
-#endif // LLVM_TARGET_TARGETINSTRINFO_H
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Tue Nov 7 17:01:31 2017
@@ -28,12 +28,12 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Analysis.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Analysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/Analysis.cpp Tue Nov 7 17:01:31 2017
@@ -15,6 +15,7 @@
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
@@ -24,7 +25,6 @@
#include "llvm/IR/Module.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/GlobalStatus.h"
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Nov 7 17:01:31 2017
@@ -51,6 +51,8 @@
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Comdat.h"
#include "llvm/IR/Constant.h"
@@ -100,8 +102,6 @@
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Tue Nov 7 17:01:31 2017
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
@@ -32,7 +33,6 @@
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 7 17:01:31 2017
@@ -39,6 +39,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -52,7 +53,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/BranchRelaxation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchRelaxation.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchRelaxation.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchRelaxation.cpp Tue Nov 7 17:01:31 2017
@@ -15,6 +15,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
@@ -22,7 +23,6 @@
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/CFIInstrInserter.cpp Tue Nov 7 17:01:31 2017
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Tue Nov 7 17:01:31 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Tue Nov 7 17:01:31 2017
@@ -26,11 +26,11 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Tue Nov 7 17:01:31 2017
@@ -29,12 +29,12 @@
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Tue Nov 7 17:01:31 2017
@@ -15,10 +15,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)
+++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Tue Nov 7 17:01:31 2017
@@ -34,12 +34,12 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/PassRegistry.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp Tue Nov 7 17:01:31 2017
@@ -30,10 +30,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 7 17:01:31 2017
@@ -15,10 +15,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp Tue Nov 7 17:01:31 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/FEntryInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/FEntryInserter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/FEntryInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/FEntryInserter.cpp Tue Nov 7 17:01:31 2017
@@ -15,10 +15,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/GCRootLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCRootLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GCRootLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCRootLowering.cpp Tue Nov 7 17:01:31 2017
@@ -18,14 +18,14 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp Tue Nov 7 17:01:31 2017
@@ -20,9 +20,9 @@
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <iterator>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Tue Nov 7 17:01:31 2017
@@ -15,8 +15,8 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue Nov 7 17:01:31 2017
@@ -19,10 +19,10 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Utils.cpp Tue Nov 7 17:01:31 2017
@@ -17,9 +17,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Constants.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#define DEBUG_TYPE "globalisel-utils"
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Nov 7 17:01:31 2017
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -40,7 +41,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp (original)
+++ llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp Tue Nov 7 17:01:31 2017
@@ -44,6 +44,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/LLVMContext.h"
@@ -51,7 +52,6 @@
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Nov 7 17:01:31 2017
@@ -41,6 +41,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/BranchProbability.h"
@@ -49,7 +50,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugValues.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugValues.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugValues.cpp Tue Nov 7 17:01:31 2017
@@ -36,6 +36,8 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -46,8 +48,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Nov 7 17:01:31 2017
@@ -39,6 +39,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -51,7 +52,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Tue Nov 7 17:01:31 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Tue Nov 7 17:01:31 2017
@@ -34,10 +34,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <algorithm>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp Tue Nov 7 17:01:31 2017
@@ -26,12 +26,12 @@
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <queue>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Tue Nov 7 17:01:31 2017
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#include "MILexer.h"
#include "MIParser.h"
+#include "MILexer.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/ArrayRef.h"
@@ -21,8 +21,8 @@
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/AsmParser/Parser.h"
#include "llvm/AsmParser/SlotMapping.h"
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
@@ -64,7 +65,6 @@
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Nov 7 17:01:31 2017
@@ -12,16 +12,18 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/None.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
+#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -31,19 +33,18 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MIRPrinter.h"
-#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/IRPrintingPasses.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
-#include "llvm/IR/IRPrintingPasses.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/IR/Value.h"
@@ -57,9 +58,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/YAMLTraits.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Nov 7 17:01:31 2017
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfoMetadata.h"
@@ -30,7 +31,6 @@
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Tue Nov 7 17:01:31 2017
@@ -43,6 +43,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/TailDuplicator.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -55,7 +56,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Nov 7 17:01:31 2017
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
@@ -35,7 +36,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/RecyclingAllocator.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCombiner.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCombiner.cpp Tue Nov 7 17:01:31 2017
@@ -21,11 +21,11 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp Tue Nov 7 17:01:31 2017
@@ -23,11 +23,11 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp Tue Nov 7 17:01:31 2017
@@ -16,10 +16,10 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Nov 7 17:01:31 2017
@@ -33,6 +33,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
@@ -58,7 +59,6 @@
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp Tue Nov 7 17:01:31 2017
@@ -13,7 +13,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Nov 7 17:01:31 2017
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -43,7 +44,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineOutliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOutliner.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineOutliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineOutliner.cpp Tue Nov 7 17:01:31 2017
@@ -65,11 +65,11 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Tue Nov 7 17:01:31 2017
@@ -89,6 +89,7 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -102,7 +103,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
@@ -28,7 +29,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Tue Nov 7 17:01:31 2017
@@ -21,11 +21,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/SSAUpdaterImpl.h"
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Nov 7 17:01:31 2017
@@ -42,6 +42,7 @@
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/LaneBitmask.h"
@@ -52,7 +53,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Tue Nov 7 17:01:31 2017
@@ -33,6 +33,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Pass.h"
@@ -40,7 +41,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Nov 7 17:01:31 2017
@@ -51,6 +51,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
@@ -66,7 +67,6 @@
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/MacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MacroFusion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MacroFusion.cpp (original)
+++ llvm/trunk/lib/CodeGen/MacroFusion.cpp Tue Nov 7 17:01:31 2017
@@ -19,10 +19,10 @@
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#define DEBUG_TYPE "machine-scheduler"
Modified: llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizePHIs.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/OptimizePHIs.cpp (original)
+++ llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Tue Nov 7 17:01:31 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 7 17:01:31 2017
@@ -31,11 +31,11 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/PatchableFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PatchableFunction.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PatchableFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/PatchableFunction.cpp Tue Nov 7 17:01:31 2017
@@ -17,7 +17,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Nov 7 17:01:31 2017
@@ -81,6 +81,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -88,7 +89,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp Tue Nov 7 17:01:31 2017
@@ -31,10 +31,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Nov 7 17:01:31 2017
@@ -34,12 +34,12 @@
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Tue Nov 7 17:01:31 2017
@@ -13,9 +13,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Tue Nov 7 17:01:31 2017
@@ -39,6 +39,8 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackProtector.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -55,8 +57,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original)
+++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Tue Nov 7 17:01:31 2017
@@ -14,7 +14,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Support/ErrorHandling.h"
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Nov 7 17:01:31 2017
@@ -30,6 +30,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Metadata.h"
@@ -41,7 +42,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Nov 7 17:01:31 2017
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
@@ -66,7 +67,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Nov 7 17:01:31 2017
@@ -35,17 +35,17 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
-#include "llvm/Pass.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Nov 7 17:01:31 2017
@@ -28,13 +28,13 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp Tue Nov 7 17:01:31 2017
@@ -35,7 +35,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Nov 7 17:01:31 2017
@@ -19,11 +19,11 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Tue Nov 7 17:01:31 2017
@@ -15,12 +15,12 @@
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Nov 7 17:01:31 2017
@@ -63,6 +63,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -98,7 +99,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Tue Nov 7 17:01:31 2017
@@ -19,6 +19,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
@@ -32,8 +34,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Nov 7 17:01:31 2017
@@ -21,12 +21,12 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Nov 7 17:01:31 2017
@@ -18,12 +18,12 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 7 17:01:31 2017
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -42,7 +43,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Nov 7 17:01:31 2017
@@ -23,11 +23,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp Tue Nov 7 17:01:31 2017
@@ -25,11 +25,11 @@
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <climits>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Nov 7 17:01:31 2017
@@ -55,6 +55,8 @@
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/Argument.h"
@@ -98,8 +100,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Tue Nov 7 17:01:31 2017
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@@ -38,7 +39,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Nov 7 17:01:31 2017
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/SelectionDAGISel.h"
#include "ScheduleDAGSDNodes.h"
#include "SelectionDAGBuilder.h"
#include "llvm/ADT/APInt.h"
@@ -45,9 +46,9 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/StackProtector.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@@ -80,7 +81,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
Modified: llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrap.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ShrinkWrap.cpp (original)
+++ llvm/trunk/lib/CodeGen/ShrinkWrap.cpp Tue Nov 7 17:01:31 2017
@@ -56,15 +56,17 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -73,8 +75,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/SlotIndexes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SlotIndexes.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SlotIndexes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SlotIndexes.cpp Tue Nov 7 17:01:31 2017
@@ -10,9 +10,9 @@
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Nov 7 17:01:31 2017
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/LaneBitmask.h"
@@ -43,7 +44,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Tue Nov 7 17:01:31 2017
@@ -28,12 +28,12 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/TailDuplicator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplicator.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplicator.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplicator.cpp Tue Nov 7 17:01:31 2017
@@ -12,13 +12,14 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/TailDuplicator.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -27,14 +28,13 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
-#include "llvm/CodeGen/TailDuplicator.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp Tue Nov 7 17:01:31 2017
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -26,7 +27,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Nov 7 17:01:31 2017
@@ -16,13 +16,13 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp Tue Nov 7 17:01:31 2017
@@ -14,11 +14,11 @@
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <string>
using namespace llvm;
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 7 17:01:31 2017
@@ -46,6 +46,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Pass.h"
@@ -54,7 +55,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp Tue Nov 7 17:01:31 2017
@@ -30,6 +30,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CFG.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Dominators.h"
@@ -37,7 +38,6 @@
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
static bool eliminateUnreachableBlock(Function &F) {
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Nov 7 17:01:31 2017
@@ -31,12 +31,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp (original)
+++ llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp Tue Nov 7 17:01:31 2017
@@ -23,10 +23,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp Tue Nov 7 17:01:31 2017
@@ -22,9 +22,9 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.h Tue Nov 7 17:01:31 2017
@@ -19,8 +19,8 @@
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CallingConv.h"
-#include "llvm/Target/TargetInstrInfo.h"
namespace {
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CondBrTuning.cpp Tue Nov 7 17:01:31 2017
@@ -34,9 +34,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp Tue Nov 7 17:01:31 2017
@@ -73,11 +73,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdlib>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp Tue Nov 7 17:01:31 2017
@@ -31,10 +31,10 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp Tue Nov 7 17:01:31 2017
@@ -20,9 +20,9 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp Tue Nov 7 17:01:31 2017
@@ -110,6 +110,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DataLayout.h"
@@ -121,7 +122,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -42,6 +42,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
@@ -71,7 +72,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetCallingConv.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Tue Nov 7 17:01:31 2017
@@ -17,7 +17,7 @@
#include "AArch64.h"
#include "AArch64RegisterInfo.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "AArch64GenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cpp Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#include "AArch64MacroFusion.h"
#include "AArch64Subtarget.h"
#include "llvm/CodeGen/MacroFusion.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp Tue Nov 7 17:01:31 2017
@@ -16,10 +16,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64VectorByElementOpt.cpp Tue Nov 7 17:01:31 2017
@@ -33,11 +33,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -18,7 +18,7 @@
#include "AMDGPU.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "AMDGPUGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Tue Nov 7 17:01:31 2017
@@ -14,15 +14,15 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
-#include "AMDGPUMachineFunction.h"
#include "AMDGPUArgumentUsageInfo.h"
+#include "AMDGPUMachineFunction.h"
#include "SIRegisterInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include <array>
Modified: llvm/trunk/lib/Target/ARC/ARCBranchFinalize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCBranchFinalize.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCBranchFinalize.cpp (original)
+++ llvm/trunk/lib/Target/ARC/ARCBranchFinalize.cpp Tue Nov 7 17:01:31 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <vector>
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARC/ARCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARC/ARCInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
#include "ARCRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "ARCGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 7 17:01:31 2017
@@ -37,6 +37,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
@@ -53,7 +54,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -21,7 +21,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include <array>
#include <cstdint>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
@@ -41,7 +42,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCallingConv.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMCallingConv.h Tue Nov 7 17:01:31 2017
@@ -19,8 +19,8 @@
#include "ARMBaseInstrInfo.h"
#include "ARMSubtarget.h"
#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CallingConv.h"
-#include "llvm/Target/TargetInstrInfo.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 7 17:01:31 2017
@@ -43,6 +43,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
@@ -72,7 +73,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Nov 7 17:01:31 2017
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
@@ -49,7 +50,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -57,6 +57,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -94,7 +95,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov 7 17:01:31 2017
@@ -41,10 +41,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -53,8 +55,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/ARM/ARMMacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMacroFusion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMacroFusion.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMacroFusion.cpp Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#include "ARMMacroFusion.h"
#include "ARMSubtarget.h"
#include "llvm/CodeGen/MacroFusion.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
namespace llvm {
Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Tue Nov 7 17:01:31 2017
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDwarf.h"
@@ -38,7 +39,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <bitset>
Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Tue Nov 7 17:01:31 2017
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -34,7 +35,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -14,7 +14,7 @@
#ifndef LLVM_AVR_INSTR_INFO_H
#define LLVM_AVR_INSTR_INFO_H
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "AVRRegisterInfo.h"
Modified: llvm/trunk/lib/Target/BPF/BPFInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFInstrInfo.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_BPF_BPFINSTRINFO_H
#include "BPFRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "BPFGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/BPF/BPFRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/BPF/BPFRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -18,10 +18,10 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#define GET_REGINFO_TARGET_DESC
#include "BPFGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp Tue Nov 7 17:01:31 2017
@@ -14,9 +14,9 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <vector>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp Tue Nov 7 17:01:31 2017
@@ -19,8 +19,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/PassSupport.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Nov 7 17:01:31 2017
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -47,7 +48,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -19,8 +19,8 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include <cstdint>
#include <vector>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Tue Nov 7 17:01:31 2017
@@ -24,12 +24,12 @@
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.h Tue Nov 7 17:01:31 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Tue Nov 7 17:01:31 2017
@@ -44,12 +44,12 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/PassSupport.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -26,13 +26,13 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp Tue Nov 7 17:01:31 2017
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp Tue Nov 7 17:01:31 2017
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -28,7 +29,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp Tue Nov 7 17:01:31 2017
@@ -17,8 +17,8 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
#include "LanaiRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "LanaiGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp Tue Nov 7 17:01:31 2017
@@ -30,8 +30,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
#define GET_INSTRMAP_INFO
Modified: llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -20,11 +20,11 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#define GET_REGINFO_TARGET_DESC
#include "LanaiGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
#include "MSP430RegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "MSP430GenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -17,8 +17,8 @@
#include "MipsRegisterInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -22,6 +22,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/Function.h"
@@ -29,8 +31,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Tue Nov 7 17:01:31 2017
@@ -37,6 +37,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
@@ -64,7 +65,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -27,8 +27,8 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
@@ -45,6 +45,8 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
@@ -62,8 +64,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -25,7 +25,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include <cstdint>
#define GET_INSTRINFO_HEADER
Modified: llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp Tue Nov 7 17:01:31 2017
@@ -28,11 +28,11 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/RecyclingAllocator.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Tue Nov 7 17:01:31 2017
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
@@ -37,7 +38,6 @@
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Intrinsics.h"
@@ -40,7 +41,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/Mips/MipsSERegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSERegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSERegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSERegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -23,6 +23,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/Function.h"
@@ -30,8 +32,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp Tue Nov 7 17:01:31 2017
@@ -20,8 +20,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MachineLocation.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -16,7 +16,7 @@
#include "NVPTX.h"
#include "NVPTXRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "NVPTXGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp Tue Nov 7 17:01:31 2017
@@ -36,7 +36,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -18,8 +18,8 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MachineLocation.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h (original)
+++ llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h Tue Nov 7 17:01:31 2017
@@ -18,7 +18,7 @@
#include "Nios2RegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "Nios2GenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp Tue Nov 7 17:01:31 2017
@@ -21,9 +21,9 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/Debug.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Nov 7 17:01:31 2017
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
@@ -53,7 +54,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 7 17:01:31 2017
@@ -51,6 +51,7 @@
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
@@ -82,7 +83,6 @@
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -16,7 +16,7 @@
#include "PPC.h"
#include "PPCRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "PPCGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -28,6 +28,8 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
@@ -37,8 +39,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cstdlib>
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
#include "RISCVRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "RISCVGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -18,9 +18,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/Support/ErrorHandling.h"
#define GET_REGINFO_TARGET_DESC
#include "RISCVGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Tue Nov 7 17:01:31 2017
@@ -19,8 +19,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
#include "SparcRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "SparcGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -20,10 +20,10 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Nov 7 17:01:31 2017
@@ -27,12 +27,12 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -20,7 +20,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include <cstdint>
#define GET_INSTRINFO_HEADER
Modified: llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZLDCleanup.cpp Tue Nov 7 17:01:31 2017
@@ -19,7 +19,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -17,7 +17,7 @@
#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
#include "WebAssemblyRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "WebAssemblyGenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp Tue Nov 7 17:01:31 2017
@@ -34,13 +34,13 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Tue Nov 7 17:01:31 2017
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
@@ -41,7 +42,6 @@
#include "llvm/IR/Value.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
Modified: llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CmovConversion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CmovConversion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CmovConversion.cpp Tue Nov 7 17:01:31 2017
@@ -57,6 +57,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCSchedule.h"
@@ -64,7 +65,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp Tue Nov 7 17:01:31 2017
@@ -55,9 +55,9 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
#define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
Modified: llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp Tue Nov 7 17:01:31 2017
@@ -22,9 +22,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
namespace llvm {
Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Nov 7 17:01:31 2017
@@ -37,11 +37,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Nov 7 17:01:31 2017
@@ -18,7 +18,7 @@
#include "X86InstrFMA3Info.h"
#include "X86RegisterInfo.h"
#include "llvm/ADT/DenseMap.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "X86GenInstrInfo.inc"
Modified: llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MacroFusion.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MacroFusion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MacroFusion.cpp Tue Nov 7 17:01:31 2017
@@ -14,8 +14,8 @@
#include "X86MacroFusion.h"
#include "X86Subtarget.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MacroFusion.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp Tue Nov 7 17:01:31 2017
@@ -23,10 +23,10 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Nov 7 17:01:31 2017
@@ -27,14 +27,14 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Modified: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp Tue Nov 7 17:01:31 2017
@@ -26,13 +26,13 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
Modified: llvm/trunk/lib/Target/X86/X86WinAllocaExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86WinAllocaExpander.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86WinAllocaExpander.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86WinAllocaExpander.cpp Tue Nov 7 17:01:31 2017
@@ -25,9 +25,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Tue Nov 7 17:01:31 2017
@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
#include "XCoreRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "XCoreGenInstrInfo.inc"
Modified: llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp?rev=317647&r1=317646&r2=317647&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp Tue Nov 7 17:01:31 2017
@@ -10,10 +10,10 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
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