[PATCH] D39595: [DAGCombine] Refactor ReduceLoadWidth

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

Hi Florian,

Thanks for the comments, I will revert the LoadedVT change.

cheers,
sam



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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7999
                               VT.getSizeInBits() - N01->getZExtValue());
+  } else if (Opc == ISD::AND) {
+    bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
----------------
fhahn wrote:
> I am probably missing something, but I am not sure if I see the real benefit of moving this code here.  It seems the visitAND was the  right place to do it, without requiring additional checks. However, it seems like there is potential to simplify the code in `visitAND`
Both visitAND and ReduceLoadWidth contained essentially the same code to generate the new load, so it seems reasonable to me to contain this logic within the sensibly named function. In D39604 I also wish to directly use this function to combine ANDs and hopefully it can more helpful when anyone else wants to do similar.


https://reviews.llvm.org/D39595