[llvm] r317286 - [AArch64][RegisterBankInfo] Add FPR16 support in value mapping.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 2 16:38:13 PDT 2017
Author: qcolombet
Date: Thu Nov 2 16:38:13 2017
New Revision: 317286
URL: http://llvm.org/viewvc/llvm-project?rev=317286&view=rev
Log:
[AArch64][RegisterBankInfo] Add FPR16 support in value mapping.
NFC.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=317286&r1=317285&r2=317286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Thu Nov 2 16:38:13 2017
@@ -14,19 +14,21 @@
namespace llvm {
RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
- // 0: FPR 32-bit value.
+ // 0: FPR 16-bit value.
+ {0, 16, AArch64::FPRRegBank},
+ // 1: FPR 32-bit value.
{0, 32, AArch64::FPRRegBank},
- // 1: FPR 64-bit value.
+ // 2: FPR 64-bit value.
{0, 64, AArch64::FPRRegBank},
- // 2: FPR 128-bit value.
+ // 3: FPR 128-bit value.
{0, 128, AArch64::FPRRegBank},
- // 3: FPR 256-bit value.
+ // 4: FPR 256-bit value.
{0, 256, AArch64::FPRRegBank},
- // 4: FPR 512-bit value.
+ // 5: FPR 512-bit value.
{0, 512, AArch64::FPRRegBank},
- // 5: GPR 32-bit value.
+ // 6: GPR 32-bit value.
{0, 32, AArch64::GPRRegBank},
- // 6: GPR 64-bit value.
+ // 7: GPR 64-bit value.
{0, 64, AArch64::GPRRegBank},
};
@@ -37,55 +39,62 @@ RegisterBankInfo::ValueMapping AArch64Ge
{nullptr, 0},
// 3-operands instructions (all binary operations should end up with one of
// those mapping).
- // 1: FPR 32-bit value. <-- This must match First3OpsIdx.
+ // 1: FPR 16-bit value. <-- This must match First3OpsIdx.
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
+ {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
+ // 4: FPR 32-bit value. <-- This must match First3OpsIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
- // 4: FPR 64-bit value.
+ // 7: FPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
- // 7: FPR 128-bit value.
+ // 10: FPR 128-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
- // 10: FPR 256-bit value.
+ // 13: FPR 256-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
- // 13: FPR 512-bit value.
+ // 16: FPR 512-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
- // 16: GPR 32-bit value.
+ // 19: GPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- // 19: GPR 64-bit value. <-- This must match Last3OpsIdx.
+ // 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
// Cross register bank copies.
- // 22: FPR 32-bit value to GPR 32-bit value. <-- This must match
+ // 25: FPR 16-bit value to GPR 16-bit (invalid). <-- This must match
// FirstCrossRegCpyIdx.
+ {nullptr, 1},
+ {nullptr, 1},
+ // 27: FPR 32-bit value to GPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
- // 24: FPR 64-bit value to GPR 64-bit value.
+ // 29: FPR 64-bit value to GPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
- // 26: FPR 128-bit value to GPR 128-bit value (invalid)
+ // 31: FPR 128-bit value to GPR 128-bit value (invalid)
{nullptr, 1},
{nullptr, 1},
- // 28: FPR 256-bit value to GPR 256-bit value (invalid)
+ // 33: FPR 256-bit value to GPR 256-bit value (invalid)
{nullptr, 1},
{nullptr, 1},
- // 30: FPR 512-bit value to GPR 512-bit value (invalid)
+ // 35: FPR 512-bit value to GPR 512-bit value (invalid)
{nullptr, 1},
{nullptr, 1},
- // 32: GPR 32-bit value to FPR 32-bit value.
+ // 37: GPR 32-bit value to FPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
- // 34: GPR 64-bit value to FPR 64-bit value. <-- This must match
+ // 39: GPR 64-bit value to FPR 64-bit value. <-- This must match
// LastCrossRegCpyIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
@@ -145,16 +154,18 @@ unsigned AArch64GenRegisterBankInfo::get
return -1;
}
if (RBIdx == PMI_FirstFPR) {
- if (Size <= 32)
+ if (Size <= 16)
return 0;
- if (Size <= 64)
+ if (Size <= 32)
return 1;
- if (Size <= 128)
+ if (Size <= 64)
return 2;
- if (Size <= 256)
+ if (Size <= 128)
return 3;
- if (Size <= 512)
+ if (Size <= 256)
return 4;
+ if (Size <= 512)
+ return 5;
return -1;
}
return -1;
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=317286&r1=317285&r2=317286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Nov 2 16:38:13 2017
@@ -87,9 +87,9 @@ AArch64RegisterBankInfo::AArch64Register
assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
{PMI_GPR32, PMI_GPR64}) &&
"PartialMappingIdx's are incorrectly ordered");
- assert(checkPartialMappingIdx(
- PMI_FirstFPR, PMI_LastFPR,
- {PMI_FPR32, PMI_FPR64, PMI_FPR128, PMI_FPR256, PMI_FPR512}) &&
+ assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
+ {PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
+ PMI_FPR256, PMI_FPR512}) &&
"PartialMappingIdx's are incorrectly ordered");
// Now, the content.
// Check partial mapping.
@@ -102,6 +102,7 @@ AArch64RegisterBankInfo::AArch64Register
CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
+ CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
@@ -121,6 +122,7 @@ AArch64RegisterBankInfo::AArch64Register
CHECK_VALUEMAP(GPR, 32);
CHECK_VALUEMAP(GPR, 64);
+ CHECK_VALUEMAP(FPR, 16);
CHECK_VALUEMAP(FPR, 32);
CHECK_VALUEMAP(FPR, 64);
CHECK_VALUEMAP(FPR, 128);
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=317286&r1=317285&r2=317286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h Thu Nov 2 16:38:13 2017
@@ -25,10 +25,10 @@ class TargetRegisterInfo;
class AArch64GenRegisterBankInfo : public RegisterBankInfo {
protected:
-
enum PartialMappingIdx {
PMI_None = -1,
- PMI_FPR32 = 1,
+ PMI_FPR16 = 1,
+ PMI_FPR32,
PMI_FPR64,
PMI_FPR128,
PMI_FPR256,
@@ -37,7 +37,7 @@ protected:
PMI_GPR64,
PMI_FirstGPR = PMI_GPR32,
PMI_LastGPR = PMI_GPR64,
- PMI_FirstFPR = PMI_FPR32,
+ PMI_FirstFPR = PMI_FPR16,
PMI_LastFPR = PMI_FPR512,
PMI_Min = PMI_FirstFPR,
};
@@ -49,10 +49,10 @@ protected:
enum ValueMappingIdx {
InvalidIdx = 0,
First3OpsIdx = 1,
- Last3OpsIdx = 19,
+ Last3OpsIdx = 22,
DistanceBetweenRegBanks = 3,
- FirstCrossRegCpyIdx = 22,
- LastCrossRegCpyIdx = 34,
+ FirstCrossRegCpyIdx = 25,
+ LastCrossRegCpyIdx = 39,
DistanceBetweenCrossRegCpy = 2
};
More information about the llvm-commits
mailing list