[PATCH] D39575: [X86] Add subtarget features prefer-avx256 and prefer-avx128 and use them to limit vector width presented by TTI

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

This patch is the first patch based on the RFC sent to llvm-dev to enable support for a prefered vector width for the vectorizer. I'll also submit a clang patch shortly to hook it up to the driver.

RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-November/118734.html

This stores the preference as an enum in the subtarget in order of increasing strictness because the autogenerated subtarget code needs to be able max the encoding values if both prefer-avx128 and prefer-avx256 are specified in any order.

>From initial experiments there's still more work to do to prevent zmm register usage, but this gives us a baseline and plumbing that we can build on.

What's the best way to test the register width output from TTI in a lit test?


https://reviews.llvm.org/D39575

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  lib/Target/X86/X86TargetTransformInfo.cpp


Index: lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.cpp
+++ lib/Target/X86/X86TargetTransformInfo.cpp
@@ -131,9 +131,9 @@
 
 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
   if (Vector) {
-    if (ST->hasAVX512())
+    if (ST->hasAVX512() && !ST->preferAVX128or256())
       return 512;
-    if (ST->hasAVX())
+    if (ST->hasAVX() && !ST->preferAVX128())
       return 256;
     if (ST->hasSSE1())
       return 128;
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -60,6 +60,11 @@
     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
   };
 
+  enum X86PreferVecWidthEnum {
+    // NOTE: Strictest constraint must have highest encoding.
+    PreferAny, Prefer256, Prefer128
+  };
+
   enum X86ProcFamilyEnum {
     Others, 
     IntelAtom,
@@ -87,6 +92,9 @@
   /// MMX, 3DNow, 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel;
 
+  /// Prefer 128-bit, 256-bit, or no preference.
+  X86PreferVecWidthEnum X86PreferVecWidth;
+
   /// True if the processor supports X87 instructions.
   bool HasX87;
 
@@ -524,6 +532,11 @@
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
   bool hasCLWB() const { return HasCLWB; }
 
+  // NOTE: Width preferences are encoded as strictest constraint having highest
+  // value.
+  bool preferAVX128() const { return X86PreferVecWidth >= Prefer128; }
+  bool preferAVX128or256() const { return X86PreferVecWidth >= Prefer256; }
+
   bool isXRaySupported() const override { return is64Bit(); }
 
   X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
Index: lib/Target/X86/X86Subtarget.cpp
===================================================================
--- lib/Target/X86/X86Subtarget.cpp
+++ lib/Target/X86/X86Subtarget.cpp
@@ -283,6 +283,7 @@
 void X86Subtarget::initializeEnvironment() {
   X86SSELevel = NoSSE;
   X863DNowLevel = NoThreeDNow;
+  X86PreferVecWidth = PreferAny;
   HasX87 = false;
   HasCMov = false;
   HasX86_64 = false;
Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -293,6 +293,13 @@
     : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
                  "Various instructions can be fused with conditional branches">;
 
+def FeaturePreferAVX128
+    : SubtargetFeature<"prefer-avx128", "X86PreferVecWidth", "Prefer128",
+                       "Prefer 128-bit AVX instructions in the vectorizer">;
+def FeaturePreferAVX256
+    : SubtargetFeature<"prefer-avx256", "X86PreferVecWidth", "Prefer256",
+                       "Prefer 256-bit AVX instructions in the vectorizer">;
+
 //===----------------------------------------------------------------------===//
 // X86 processors supported.
 //===----------------------------------------------------------------------===//


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