[llvm] r317134 - [X86] Use foreach in X86.td to combine some of the CPU names that are obviously aliases. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 1 15:15:49 PDT 2017
Author: ctopper
Date: Wed Nov 1 15:15:49 2017
New Revision: 317134
URL: http://llvm.org/viewvc/llvm-project?rev=317134&view=rev
Log:
[X86] Use foreach in X86.td to combine some of the CPU names that are obviously aliases. NFC
Modified:
llvm/trunk/lib/Target/X86/X86.td
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=317134&r1=317133&r2=317134&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Wed Nov 1 15:15:49 2017
@@ -327,14 +327,18 @@ def : Proc<"i486", [FeatureX8
def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
-def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
-def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
+
+foreach P = ["i686", "pentiumpro"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
+}
+
def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
FeatureCMOV, FeatureFXSR]>;
-def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE1, FeatureFXSR]>;
-def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE1, FeatureFXSR]>;
+
+foreach P = ["pentium3", "pentium3m"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
+ FeatureFXSR]>;
+}
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
// The intent is to enable it for pentium4 which is the current default
@@ -350,13 +354,11 @@ def : ProcessorModel<"pentium-m", Generi
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
FeatureSSE2, FeatureFXSR]>;
-def : ProcessorModel<"pentium4", GenericPostRAModel,
- [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR]>;
-
-def : ProcessorModel<"pentium4m", GenericPostRAModel,
- [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR]>;
+foreach P = ["pentium4", "pentium4m"] in {
+ def : ProcessorModel<P, GenericPostRAModel,
+ [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
+ FeatureSSE2, FeatureFXSR]>;
+}
// Intel Quark.
def : Proc<"lakemont", []>;
@@ -665,45 +667,31 @@ def : CannonlakeProc<"cannonlake">;
def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
-def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
- FeatureSlowSHLD]>;
-def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
- FeatureSlowSHLD]>;
-def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
-def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
-def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
-def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
- Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowSHLD]>;
-def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
- Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowSHLD]>;
-def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
- Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowSHLD]>;
-def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
- Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowSHLD]>;
-def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
- Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowSHLD]>;
-def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
- Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowSHLD]>;
-def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
- Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowSHLD]>;
-def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA,
- FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowSHLD,
- FeatureLAHFSAHF]>;
-def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA,
- FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowSHLD,
- FeatureLAHFSAHF]>;
+
+foreach P = ["athlon", "athlon-tbird"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowSHLD]>;
+}
+
+foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
+ Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
+}
+
+foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
+ FeatureFXSR, Feature64Bit, FeatureSlowSHLD]>;
+}
+
+foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
+}
+
+foreach P = ["amdfam10", "barcelona"] in {
+ def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
+ FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureSlowSHLD, FeatureLAHFSAHF]>;
+}
// Bobcat
def : Proc<"btver1", [
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