[PATCH] D39089: [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

Apart from the one comment about identifying the register as SVE specific, the patch looks good.



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Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:844
+    return (Kind == k_SVERegister ||
+            (Kind == k_Register && Reg.Kind == RegKind::SVEDataVector)) &&
+           AArch64MCRegisterClasses[Class].contains(getReg());
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rengolin wrote:
> To @javed.absar comment in D39088, this may be simplified by having all done at the RegKind level, instead of having multiple types of registers on top of multiple types of SVE vectors.
I'm confused now. Why do we need both ways of identifying an SVE register?

I can't see anything in this patch that needs `k_SVEDataRegister`. All uses of it could very well be together with `k_Register` and have an additional check for `RegKind::SVEDataVector`.


https://reviews.llvm.org/D39089