[llvm] r317038 - AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
Marek Olsak via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 31 14:06:42 PDT 2017
Author: mareko
Date: Tue Oct 31 14:06:42 2017
New Revision: 317038
URL: http://llvm.org/viewvc/llvm-project?rev=317038&view=rev
Log:
AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
Summary:
Apps that benefit:
- alien isolation
- bioshock infinite
- civilization: beyond earth
- company of heroes 2
- dirt showdown
- dota 2
- F1 2015
- grid autosport
- hitman
- legend of grimrock
- serious sam 3: bfe
- shadow warrior
- talos principle
- total war: warhammer
- UE4 demos: effects cave, elemental, sun temple
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D38914
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/smrd.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp?rev=317038&r1=317037&r2=317038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp Tue Oct 31 14:06:42 2017
@@ -169,7 +169,6 @@ private:
bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
- bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
@@ -1466,13 +1465,6 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBuffe
return !Imm && isa<ConstantSDNode>(Offset);
}
-bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
- SDValue &Offset) const {
- bool Imm;
- return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
- !isa<ConstantSDNode>(Offset);
-}
-
bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
SDValue &Base,
SDValue &Offset) const {
Modified: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td?rev=317038&r1=317037&r2=317038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td Tue Oct 31 14:06:42 2017
@@ -878,13 +878,6 @@ def BUFFER_WBINVL1_VOL : MUBUF_Invalidat
// MUBUF Patterns
//===----------------------------------------------------------------------===//
-// Offset in an 32-bit VGPR
-def : GCNPat <
- (SIload_constant v4i32:$sbase, i32:$voff),
- (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, (i32 0), 0, 0, 0, 0)
->;
-
-
//===----------------------------------------------------------------------===//
// buffer_load/store_format patterns
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=317038&r1=317037&r2=317038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Tue Oct 31 14:06:42 2017
@@ -3709,6 +3709,27 @@ void SIInstrInfo::moveToVALU(MachineInst
splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32);
Inst.eraseFromParent();
continue;
+
+ case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR: {
+ unsigned VDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+
+ BuildMI(*MBB, Inst, Inst.getDebugLoc(),
+ get(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), VDst)
+ .add(*getNamedOperand(Inst, AMDGPU::OpName::soff)) // vaddr
+ .add(*getNamedOperand(Inst, AMDGPU::OpName::sbase)) // srsrc
+ .addImm(0) // soffset
+ .addImm(0) // offset
+ .addImm(getNamedOperand(Inst, AMDGPU::OpName::glc)->getImm())
+ .addImm(0) // slc
+ .addImm(0) // tfe
+ .setMemRefs(Inst.memoperands_begin(), Inst.memoperands_end());
+
+ MRI.replaceRegWith(getNamedOperand(Inst, AMDGPU::OpName::sdst)->getReg(),
+ VDst);
+ addUsersToMoveToVALUWorklist(VDst, MRI, Worklist);
+ Inst.eraseFromParent();
+ continue;
+ }
}
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
Modified: llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SMInstructions.td?rev=317038&r1=317037&r2=317038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SMInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SMInstructions.td Tue Oct 31 14:06:42 2017
@@ -239,7 +239,6 @@ def SMRDImm32 : ComplexPattern<i64
def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
-def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
multiclass SMRD_Pattern <string Instr, ValueType vt> {
@@ -282,7 +281,7 @@ def SM_LOAD_PATTERN : GCNPat < // name
// 2. Offset loaded in an 32bit SGPR
def : GCNPat <
- (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
+ (SIload_constant v4i32:$sbase, i32:$offset),
(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0)
>;
Modified: llvm/trunk/test/CodeGen/AMDGPU/smrd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smrd.ll?rev=317038&r1=317037&r2=317038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/smrd.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/smrd.ll Tue Oct 31 14:06:42 2017
@@ -175,6 +175,22 @@ main_body:
ret void
}
+; GCN-LABEL: {{^}}smrd_sgpr_offset:
+; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4
+define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 {
+main_body:
+ %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset)
+ ret float %r
+}
+
+; GCN-LABEL: {{^}}smrd_vgpr_offset:
+; GCN: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;
+define amdgpu_ps float @smrd_vgpr_offset(<4 x i32> inreg %desc, i32 %offset) #0 {
+main_body:
+ %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset)
+ ret float %r
+}
+
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
More information about the llvm-commits
mailing list