[llvm] r316864 - [X86] Add a slow-incdec command line to atomic-eflags-reuse.ll
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 29 10:15:09 PDT 2017
Author: ctopper
Date: Sun Oct 29 10:15:09 2017
New Revision: 316864
URL: http://llvm.org/viewvc/llvm-project?rev=316864&view=rev
Log:
[X86] Add a slow-incdec command line to atomic-eflags-reuse.ll
I believe the test_sub_1_cmp_1_setcc_ugt test case is being miscompiled in the fast inc/dec case.
Modified:
llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
Modified: llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll?rev=316864&r1=316863&r2=316864&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic-eflags-reuse.ll Sun Oct 29 10:15:09 2017
@@ -1,13 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=CHECK --check-prefix=FASTINCDEC
+; RUN: llc < %s -mtriple=x86_64-- -mattr=slow-incdec | FileCheck %s --check-prefix=CHECK --check-prefix=SLOWINCDEC
define i32 @test_add_1_cmov_slt(i64* %p, i32 %a0, i32 %a1) #0 {
-; CHECK-LABEL: test_add_1_cmov_slt:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock incq (%rdi)
-; CHECK-NEXT: cmovgl %edx, %esi
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_add_1_cmov_slt:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock incq (%rdi)
+; FASTINCDEC-NEXT: cmovgl %edx, %esi
+; FASTINCDEC-NEXT: movl %esi, %eax
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_add_1_cmov_slt:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
+; SLOWINCDEC-NEXT: cmovgl %edx, %esi
+; SLOWINCDEC-NEXT: movl %esi, %eax
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
%tmp1 = icmp slt i64 %tmp0, 0
@@ -16,12 +24,19 @@ entry:
}
define i32 @test_add_1_cmov_sge(i64* %p, i32 %a0, i32 %a1) #0 {
-; CHECK-LABEL: test_add_1_cmov_sge:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock incq (%rdi)
-; CHECK-NEXT: cmovlel %edx, %esi
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_add_1_cmov_sge:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock incq (%rdi)
+; FASTINCDEC-NEXT: cmovlel %edx, %esi
+; FASTINCDEC-NEXT: movl %esi, %eax
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_add_1_cmov_sge:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
+; SLOWINCDEC-NEXT: cmovlel %edx, %esi
+; SLOWINCDEC-NEXT: movl %esi, %eax
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
%tmp1 = icmp sge i64 %tmp0, 0
@@ -87,16 +102,27 @@ entry:
}
define i32 @test_add_1_brcond_sge(i64* %p, i32 %a0, i32 %a1) #0 {
-; CHECK-LABEL: test_add_1_brcond_sge:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock incq (%rdi)
-; CHECK-NEXT: jle .LBB6_2
-; CHECK-NEXT: # BB#1: # %t
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB6_2: # %f
-; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_add_1_brcond_sge:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock incq (%rdi)
+; FASTINCDEC-NEXT: jle .LBB6_2
+; FASTINCDEC-NEXT: # BB#1: # %t
+; FASTINCDEC-NEXT: movl %esi, %eax
+; FASTINCDEC-NEXT: retq
+; FASTINCDEC-NEXT: .LBB6_2: # %f
+; FASTINCDEC-NEXT: movl %edx, %eax
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_add_1_brcond_sge:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
+; SLOWINCDEC-NEXT: jle .LBB6_2
+; SLOWINCDEC-NEXT: # BB#1: # %t
+; SLOWINCDEC-NEXT: movl %esi, %eax
+; SLOWINCDEC-NEXT: retq
+; SLOWINCDEC-NEXT: .LBB6_2: # %f
+; SLOWINCDEC-NEXT: movl %edx, %eax
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
%tmp1 = icmp sge i64 %tmp0, 0
@@ -193,11 +219,17 @@ entry:
}
define i8 @test_sub_1_cmp_1_setcc_eq(i64* %p) #0 {
-; CHECK-LABEL: test_sub_1_cmp_1_setcc_eq:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock decq (%rdi)
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_eq:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock decq (%rdi)
+; FASTINCDEC-NEXT: sete %al
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_eq:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
+; SLOWINCDEC-NEXT: sete %al
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
%tmp1 = icmp eq i64 %tmp0, 1
@@ -206,11 +238,17 @@ entry:
}
define i8 @test_sub_1_cmp_1_setcc_ne(i64* %p) #0 {
-; CHECK-LABEL: test_sub_1_cmp_1_setcc_ne:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock decq (%rdi)
-; CHECK-NEXT: setne %al
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_ne:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock decq (%rdi)
+; FASTINCDEC-NEXT: setne %al
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_ne:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
+; SLOWINCDEC-NEXT: setne %al
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
%tmp1 = icmp ne i64 %tmp0, 1
@@ -219,11 +257,17 @@ entry:
}
define i8 @test_sub_1_cmp_1_setcc_ugt(i64* %p) #0 {
-; CHECK-LABEL: test_sub_1_cmp_1_setcc_ugt:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: lock decq (%rdi)
-; CHECK-NEXT: seta %al
-; CHECK-NEXT: retq
+; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_ugt:
+; FASTINCDEC: # BB#0: # %entry
+; FASTINCDEC-NEXT: lock decq (%rdi)
+; FASTINCDEC-NEXT: seta %al
+; FASTINCDEC-NEXT: retq
+;
+; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_ugt:
+; SLOWINCDEC: # BB#0: # %entry
+; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
+; SLOWINCDEC-NEXT: seta %al
+; SLOWINCDEC-NEXT: retq
entry:
%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
%tmp1 = icmp ugt i64 %tmp0, 1
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