[PATCH] D39400: WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand.

[Geoff Berry via Phabricator via llvm-commits]

gberry created this revision.
Herald added a subscriber: javed.absar.

Add isRenamable() predicate to MachineOperand.  This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand.  Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).


https://reviews.llvm.org/D39400

Files:
  include/llvm/CodeGen/MachineOperand.h
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/RegAllocFast.cpp
  lib/CodeGen/VirtRegMap.cpp
  test/CodeGen/AArch64/arm64-csldst-mmo.ll
  test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
  test/CodeGen/AArch64/arm64-misched-multimmo.ll
  test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
  test/CodeGen/ARM/Windows/vla-cpsr.ll
  test/CodeGen/PowerPC/byval-agg-info.ll
  test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
  test/CodeGen/PowerPC/quadint-return.ll
  test/CodeGen/X86/misched-copy.ll
  test/CodeGen/X86/pr28560.ll
  test/CodeGen/X86/remat-phys-dead.ll

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